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WATCHDOG TIMER/TIME-BASE TIMER/WATCH TIMER (SUB-CLOCK)
This chapter explains the watchdog timer, time-base timer and watch timer (sub-clock).
9.1 Overview of Watchdog Timer, Time-base Timer, and Watch timer
The circuit configuration of the watchdog timer, time-base timer, and watch timer are shown below.
• Watchdog timer: Watchdog counter, control register, and watchdog reset circuit
• Time-base timer: 18-bit timer, and circuit to control interrupt that occurs at interval
• Watch timer: 15-bit timer, and circuit to control interrupt that occurs at interval
n Watchdog timer function
The watchdog timer is composed of 2-bit watchdog counter using carrying-up signals of 18-bit time-base
timer or 15-bit watch timer as clock source, control register, and watchdog reset control unit.
When the watchdog timer is not cleared within a certain period of timer after being started, the CPU is reset.
• Time-base timer function
The time-base timer is an 18-bit free-run counter (time-base counter) that increments in synchronization
with the internal count clock (2-divided original oscillation), and has an interval timer function that can be
selected from four types of interval times. Also, the time-base timer has a function to supply the operating
clock to timer output of the oscillation stabilization wait time, and the watchdog timer. The time-base timer
uses the main clock, irrespective of the MCS and SCS bits in CKSCR.
• Watch timer function
The watch timer has a timer function for the oscillation stabilization wait time for the clock source of the
watchdog timer and sub-clock, and an interval timer function that generates interrupts at a certain cycle.
The watch timer uses the sub-clock, irrespective of the MCS and SCS bits in CKSCR.
9-3
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