Notes On Using Timebase Timer - Fujitsu F2MC-8L Series Hardware Manual

5.6

Notes on Using Timebase Timer

This section lists points to note when using the timebase timer.
Notes on Using Timebase Timer
Notes on setting bits by program
The system cannot recover from interrupt processing if the overflow interrupt request flag bit
(TBTC: TBOF) is "1" and the interrupt request enable bit is enabled (TBTC: TBIE = "1"). Always
clear the TBOF bit.
Clearing timebase timer
In addition to being cleared by the timebase timer initialization bit (TBTC: TBR = "0"), the timer
is cleared whenever the main clock oscillation stabilization delay time is required. When the
timebase timer has been selected as the count clock for the watchdog timer (WDTC: CS = 0),
clearing the timebase timer also clears the watchdog timer.
Using as timer for oscillation stabilization delay time
As the main clock source oscillation is stopped when the power is turned on and during main-
stop mode or subclock mode, the timebase timer provides the oscillation stabilization delay time
for the main clock after the oscillator starts.
An appropriate oscillation stabilization delay time must be selected for the type of resonator
connected to the main clock oscillator (clock generator).
Reference:
See Section 3.6.1, "Oscillation Stabilization Delay Time" for details.
Notes on peripheral functions that receive a clock supply from timebase timer
In any mode in which the main clock stops oscillation, the counter is cleared and the timebase
timer stops operation. Besides, as the clock derived from the timebase timer restarts output
from its initial state when the timebase timer counter is cleared, the "H" level may be shorter or
the "L" level longer by a maximum of half cycle. The clock of the watchdog timer also restarts
output from its initial state. However, as the watchdog timer counter is cleared at the same time,
the watchdog timer operates in normal cycle.
5.6 Notes on Using Timebase Timer
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