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CHAPTER 11 MULTIFUNCTIONAL TIMER
11.7
Notes on Using Multifunctional Timer
Heed the following cautions when using the multifunctional timer.
■ Notes on Using 16-bit Free-Run Timer
●
Cautions for setting via the program
• When a reset is executed, although the timer value becomes "0000
not set.
• Since the timer-mode bit (TCCSL register MODE: bit5) has a buffer, and so timer modes changed after
zero detection are enabled.
• A software clear (TCCSL register SCLR: bit4 = 1) initializes the timer. At this time, if the timer-count
clock is the machine cycle (φ), zero-detection interrupts are not generated. If the timer-count clock is a
division of the machine cycle (φ), zero-detection interrupts are generated.
• When the compare value and count value match, if the count starts, the compare-clear flag is not set.
●
Note on interruption
• If "1" is set in the timer status control register higher-order (TCCSH) IRQZF: bit14, then interrupt
requests are enabled (TCCSH register IRQZE: bit13 = 1), control cannot return from interrupt
processing. IRQZF: Always clear bit14.
• If "1" is set in the timer status control register higher-order (TCCSH) ICLR: bit9, then interrupt requests
are enabled (TCCSH register ICRE: bit8 = 1), control cannot return from interrupt processing.
ICLR: Always clear bit9.
■ Notes on Using 16-bit Output Compare
●
Note on interruption
If "11
" is set in the compare control register lower-order (OCSL0, OCSL2, and OCSL4) IOP1, IOP0: bit7
B
and bit6, then interrupt requests are enabled (OCSL register IOE1, IOE0: bit6 and bit5 = 11
cannot return from interrupt processing. Always clear the IOP0, IOP1 bits.
■ Cautions for Use of 16-bit Input Capture
●
Note on interruption
• If "1" is set in the input capture-status control register's lower-order (PICSL01 and ICSL23) ICP3, ICP2,
ICP1, and ICP0 (bit7 and bit6 of both), then interrupt requests are enabled (PCICSL01 and ICSL23
registers' ICE3, ICE2, ICE1, and ICE0 (bit5 and bit4 of both) = 11
interrupt processing. Be sure to clear ICP3, ICP2, ICP1, and 0 (both bit7 and bit6).
• If the level of the input capture pin (IC) changes between the time that ICP bit3, bit2, bit1, and bit0 are
set, and the interrupt routine is processed, then the ICP3 and ICP2 valid edge specification bits (ICSH
23 register's IEI3, IEI2: bit9 and bit8) will indicate the last edge detected.
Note:
There are no ICP1, ICP0 valid edge specification bits.
292
", the zero-detection interrupt flag is
H
), control cannot return from
B
), control
B
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