Block Diagram Of Low-Power Consumption Control Circuit - Fujitsu F2MC-16LX Hardware Manual

6.2

Block Diagram of Low-power Consumption Control Circuit

The low-power consumption control circuit is composed of the following seven blocks.
• CPU intermittent operation selector
• Standby controller circuit
• CPU clock controller circuit
• Peripheral clock controller circuit
• Pin high-impedance controller circuit
• Internal reset generator circuit
• Low-power consumption mode control register (LPMCR)
Block Diagram of Low-power Consumption Control Circuit
Figure 6.2-1 shows the block diagram of the low-power consumption control circuit.
Figure 6.2-1 Block Diagram of Low-power Consumption Control Circuit
RST
Reset (Cancellation)
Interrupt (Cancellation)
Clock
generation
unit
Pin
X0
X1
Pin
Pin
X0A
X1A
Pin
Low power consumption mode control register (LPMCR)
STP SLP SPL RST TMD
Pin
2
Operation
clock
selector
PLL frequency
SCM MCM
multiplication circuit
Clock selection register (CKSCR)
2
-division
Main
Oscillation clock
clock
(HCLK)
Oscillation clock
Sub clock
generation circuit
(SCLK)
4
-division
System clock
generation circuit
CHAPTER 6 LOW-POWER CONSUMPTION MODE
CG1 CG0
Reserved
Pin high
impedance
control circuit
Internal reset
generation
circuit
CPU intermittent
operation sector
CPU clock
control circuit
Standby
control circuit
Oscillation stable
wait cancellation
Sub clock oscillation stabilization wait cancellation
Main clock oscillation stabilization wait cancellation
Machine
clock
2
2
WS1 WS0 SCS MCS CS1 CS0
512 4 2 2
-division -division -division -division
Timebase timer
1024 8
-division -division
Watch timer
Pin Hi-Z
control
Internal reset
Intermittent cycle
selection
CPU clock
Watch, Stop, Sleep signal
Watch, Stop signal
Peripheral
clock
control circuit
Oscillation
stable wait
time
selector
2 2 2 4
-division -division -division -division
to Watchdog timer
2 2
-division -division
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