Block Diagram; Figure 6.2A Low-Power Consumption Control Circuit And Clock Generator - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

6.2 Block Diagram

6.2 Block Diagram
CKSCR
SCM
SCS
CKSCR
MCM
MCS
CKSCR
CS1
CS0
LPMCR
CG1
CG0
LPMCR
SLP
STP
TMD
CKSCR
WS1
WS0
LPMCR
SPL
SSR
LPMCR
RST

Figure 6.2a Low-power consumption control circuit and clock generator

62 Chapter 6: Low Power Control Circuit
Subclock switching
controller
PLL multiplier circuit
1 2 3 4
1/2 S
CPU clock selector
CPU intermittent
operation function
cycle number
selection circuit
SCM SLEEP
Standby MSTP
Control circuit STOP
RST Cancel HST start
Oscillation
stabilization
wait time
selector
Pin high-impedance
control circuit
Self-refresh control circuit
Internal reset
generation circuit
CPU system
clock
generation
Peripheral
system clock
generation
4
Clock input
2
13
2
Timebase timer
15
2
18
2
12 14 16 19
2 2 2 2
Subclock
(OSC oscillation)
Main clock
(OSC oscillation)
CPU clock
0/9/17/33 intermittent
cycle selection
Peripheral clock
Main OSC stop
Sub OSC stop
HSTX pin
Interrupt request
or RST
Pin HI-Z
Self-refresh
RSTX pin
Internal RST
To watchdog timer
WDGRST
MB90580 Series