ST STM32G0 1 Series Reference Manual page 1375

RM0444
The register is asynchronously reset by the POR (and not the system reset). It can be
written by the debugger under system reset.
Address offset: 0x08
Power on reset (POR): 0x0000 0000 (not reset by system reset)
Only 32-bit access are supported.
31 30 29
rw rw
15 14 13
1. Only significant on devices integrating I2C2, otherwise reserved. Refer to
2. Only significant on devices integrating TIM4, otherwise reserved. Refer to
Bit 31 DBG_LPTIM1_STOP: Clocking of LPTIMER1 counter when the core is halted
This bit enables/disables the clock to the counter of LPTIMER1 when the core is halted:
0: Enable
1: Disable
Bit 30 DBG_LPTIM2_STOP: Clocking of LPTIMER2 counter when the core is halted
This bit enables/disables the clock to the counter of LPTIMER2 when the core is halted:
0: Enable
1: Disable
Bits 29:23 Reserved, must be kept at reset value.
Bit 22 DBG_I2C2_SMBUS_TIMEOUT: SMBUS timeout when core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bit 21 DBG_I2C1_SMBUS_TIMEOUT: SMBUS timeout when core is halted
0: Same behavior as in normal mode
1: The SMBUS timeout is frozen
Bits 20:13 Reserved, must be kept at reset value.
28 27 26 25
12 11 10 9
rw rw rw
24 23 22
rw
8 7 6
Section 1.4: Availability of
Section 1.4: Availability of
RM0444 Rev 5
Debug support (DBG)
21 20 19 18
rw
5 4 3 2
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peripherals.
peripherals.
17 16
1 0
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