ST STM32G0 1 Series Reference Manual page 1361

RM0444
Bits 31:13 Reserved, must be kept at reset value.
Bit 12 TXACKE: Tx-missing acknowledge error
In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was
received. In case of broadcast transmission, TXACKE informs application that a negative
acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM
controls.
TXACKE is cleared by software write at 1.
Bit 11 TXERR: Tx-error
In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the
CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM
controls.
TXERR is cleared by software write at 1.
Bit 10 TXUDR: Tx-buffer underrun
In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before
of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM
control bits.
TXUDR is cleared by software write at 1
Bit 9 TXEND: End of transmission
TXEND is set by hardware to inform application that the last byte of the CEC message has been
successfully transmitted. TXEND clears the TXSOM and TXEOM control bits.
TXEND is cleared by software write at 1.
Bit 8 TXBR: Tx-byte request
TXBR is set by hardware to inform application that the next transmission data has to be written to
TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the
next byte to TXDR within six nominal data-bit periods before transmission underrun error occurs
(TXUDR).
TXBR is cleared by software write at 1.
Bit 7 ARBLST: Arbitration lost
ARBLST is set by hardware to inform application that CEC device is switching to reception due to
arbitration lost event following the TXSOM command. ARBLST can be due either to a contending
CEC device starting earlier or starting at the same time but with higher HEADER priority. After
ARBLST assertion TXSOM bit keeps pending for next transmission attempt.
ARBLST is cleared by software write at 1.
Bit 6 RXACKE: Rx-missing acknowledge
In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen
on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not
directly addressed messages (destination address not enabled in OAR). RXACKE aborts message
reception.
RXACKE is cleared by software write at 1.
Bit 5 LBPE: Rx-long bit period error
LBPE is set by hardware in case a data-bit waveform is detected with long bit period error. LBPE is
set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still
longing. LBPE always stops reception of the CEC message. LBPE generates an error-bit on the
CEC line if LBPEGEN = 1. In case of broadcast, error-bit is generated even in case of
LBPEGEN = 0.
LBPE is cleared by software write at 1.
RM0444 Rev 5
HDMI-CEC controller (CEC)
1361/1390
1364