ST STM32G0 1 Series Reference Manual page 1383

RM0444
Date Revision
19-May-2020
Table 256. Document revision history (continued)
– Empty check
– Section 3.3.8: FLASH Main memory programming sequences
– User and read protection option bytes
– Option byte loading
– Table 19: Access status versus protection level and execution modes
– Section 3.5.4: Securable memory area
– Section 3.7.1: FLASH access control register (FLASH_ACR)
– Section 3.7.8: FLASH option register (FLASH_OPTR)
swapped with BORF_LEV[1:0]
– Section 3.7.9: FLASH PCROP area A start address register
(FLASH_PCROP1ASR)
address register
– Section 7.3: GPIO functional
– Section 7.3.15: USB PD / Dead battery
– Table 48: Programmable data width and endian behavior (when
PINC = MINC =
– Table 52: DMAMUX: assignment of multiplexer inputs to
TIM16/17_TRG_COM corrected to TIM16/17_COM
– Section 15.2: ADC main
– Section 15.3.1: ADC pins and internal
(External triggers table brought to this section)
– Table 71: Latency between trigger and start of
3
– Section : Calculating the actual V
voltage - corrected from V
– Section 20: AES hardware accelerator
– Section 21: Advanced-control timer
– Figure 187: Capture/Compare channel 1 main circuit
stage of Capture/Compare channel (channel 1)
– Figure 205: Master/slave connection example with 1 channel only timers
added
– Table 120: Output control bit for standard OCx channels
– Section 22.4.29: TIM3 timer input selection register
TI4SEL[3:0] and TI3SEL[3:0]
– Figure 221: General-purpose timer block diagram
– Figure 232: Capture/compare channel 1 main circuit
stage of capture/compare channel (channel 1)
– Section 24.3.11: Using timer output as trigger for other timers (TIM14)
– Figure 251: Capture/compare channel 1 main circuit
– Section 25.4.23: Using timer output as trigger for other timers
(TIM16/TIM17)
– Former Section 28.3.4 Advanced watchdog interrupt feature moved to
Section 29.4: WWDG interrupts
– Section 32.4.3: I2C pins and internal signals
– Section 32.7.3: I2C own address 1 register (I2C_OAR1)
I2C interrupt clear register (I2C_ICR)
RM0444 Rev 5
Changes
section
section
to Section 3.7.14: FLASH PCROP area B end
(FLASH_PCROP1BER): reset values
description: introductory information modified
1): NDT in the first row corrected from 8 to 4
features: V
TS
REF+
to V
DDA REF+
(TIM1): general update
added
Revision history
section
(BORR_LEV[1:0]
support: description filled
resources:
corrected to V
SENSE
signals: tables and their organization
conversion: latency values
voltage using the internal reference
(AES): general update
and Figure 188: Output
updated
updated
(TIM3_TISEL): removed
(TIM14): updated
and Figure 233: Output
updated
updated
added
and Section 32.7.8:
updated
added
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