ST STM32G0 1 Series Reference Manual page 1334

USB Type-C™ / USB Power Delivery interface (UCPD)
Bits 8:7 ANASUBMODE[1:0]: Analog PHY sub-mode
Refer to
TYPEC_VSTATE_CCx
Bit 6 PHYCCSEL: CC1/CC2 line selector for USB Power Delivery signaling
0: Use CC1 IO for Power Delivery communication
1: Use CC2 IO for Power Delivery communication
The selection depends on the cable orientation as discovered at attach.
Bit 5 PHYRXEN: USB Power Delivery receiver enable
0: Disable
1: Enable
Both CC1 and CC2 receivers are disabled when the bit is cleared. Only the CC receiver
selected via the PHYCCSEL bit is enabled when the bit is set.
Bit 4 RXMODE: Receiver mode
Determines the mode of the receiver.
0: Normal receive mode
1: BIST receive mode (BIST test data mode)
When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the
CRC checking still proceeds as for a normal message.
Bit 3 TXHRST: Command to send a Tx Hard Reset
0: No effect
1: Start Tx Hard Reset message
The bit is cleared by hardware as soon as the message transmission begins or is discarded.
Bit 2 TXSEND: Command to send a Tx packet
0: No effect
1: Start Tx packet transmission
The bit is cleared by hardware as soon as the packet transmission begins or is discarded.
Bits 1:0 TXMODE[1:0]: Type of Tx packet
Writing the bitfield triggers the action as follows, depending on the value:
0x0: Transmission of Tx packet previously defined in other registers
0x1: Cable Reset sequence
0x2: BIST test sequence (BIST Carrier Mode 2)
Others: invalid
From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST
Carrier Mode 2. To quit this mode correctly (after the "tBISTContMode" delay), disable the
peripheral (UCPDEN = 0).
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Table 237: Coding for ANAMODE, ANASUBMODE and link with
for the effect of this bitfield.
RM0444 Rev 5
RM0444