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8XC196NT USER'S MANUAL
6.3.5
Design Considerations for External Interrupt Inputs
To configure a port pin that serves as an external interrupt input, you must set the corresponding
bits in the configuration registers (Px_DIR, Px_MODE, and Px_REG). To configure P2.2/EX-
TINT as an external interrupt input, we recommend the following sequence to prevent a false in-
terrupt request:
1.
Disable interrupts by executing the DI instruction.
2.
Set P2_DIR.2.
3.
Set P2_MODE.2.
4.
Set P2_REG.2.
5.
Clear INT_PEND1.6.
6.
Enable interrupts (optional) by executing the EI instruction.
6.4
BIDIRECTIONAL PORTS 3 AND 4 (ADDRESS/DATA BUS)
Ports 3 and 4 are eight-bit, bidirectional, memory-mapped I/O ports. They can be addressed only
with indirect or indexed addressing and cannot be windowed. Ports 3 and 4 provide the multi-
plexed address/data bus. In programming modes, ports 3 and 4 serve as the programming bus
(PBUS). Port 3 can also serve as the slave port. Port 5 supplies the bus-control signals.
During external memory bus cycles, the processor takes control of ports 3 and 4 and automatical-
ly configures them as complementary output ports for driving address/data or as inputs for read-
ing data. For this reason, these ports have no mode registers.
Systems with EA# tied inactive have idle time between external bus cycles. When the address/da-
ta bus is idle, you can use the ports for I/O. Like port 5, these ports use standard CMOS input
buffers. However, ports 3 and 4 must be configured entirely as complementary or open-drain
ports; their pins cannot be configured individually. Systems with EA# tied active cannot use ports
3 and 4 as standard I/O; when EA# is active, these ports will function only as the address/data bus.
Table 6-11 lists the port 3 and 4 pins with their special-function signals and associated peripher-
als. Table 6-12 lists the registers that affect the function and indicate the status of ports 3 and 4.
6-14
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