Dma Low Interrupt Flag Clear Register (Dma_Lifcr); Dma High Interrupt Flag Clear Register (Dma_Hifcr) - ST STM32F207 Series Reference Manual

DMA controller (DMA)
9.5.3

DMA low interrupt flag clear register (DMA_LIFCR)

Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28 27
CTCIF3 CHTIF3 CTEIF3 CDMEIF3
Reserved
w
15 14 13 12 11
CTCIF1 CHTIF1 CTEIF1 CDMEIF1
Reserved
w
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 CTCIFx: Stream x clear transfer complete interrupt flag (x = 3..0)
Bits 26, 20, 10, 4 CHTIFx: Stream x clear half transfer interrupt flag (x = 3..0)
Bits 25, 19, 9, 3 CTEIFx: Stream x clear transfer error interrupt flag (x = 3..0)
Bits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 3..0)
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 3..0)
9.5.4

DMA high interrupt flag clear register (DMA_HIFCR)

Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29 28 27
CTCIF7 CHTIF7 CTEIF7 CDMEIF7
Reserved
w
15 14 13 12 11
CTCIF5 CHTIF5 CTEIF5 CDMEIF5
Reserved
w
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 CTCIFx: Stream x clear transfer complete interrupt flag (x = 7..4)
Bits 26, 20, 10, 4 CHTIFx: Stream x clear half transfer interrupt flag (x = 7..4)
Bits 25, 19, 9, 3 CTEIFx: Stream x clear transfer error interrupt flag (x = 7..4)
200/1381
26 25 24
w w w
10 9 8
w w w
Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_LISR register
Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_LISR register
Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_LISR register
Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_LISR register
Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_LISR register
26 25 24
w w w
10 9 8
w w w
Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register
Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_HISR register
Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_HISR register
23 22 21
CFEIF3 CTCIF2
Reserved
w w
7 6 5
CFEIF1 CTCIF0
Reserved
w w
23 22 21
CFEIF7 CTCIF6
Reserved
w w
7 6 5
CFEIF5 CTCIF4
Reserved
w w
RM0033 Rev 9
20 19 18
CHTIF2 CTEIF2 CDMEIF2
w w w
4 3 2
CHTIF0 CTEIF0 CDMEIF0
w w w
20 19 18
CHTIF6 CTEIF6 CDMEIF6
w w w
4 3 2
CHTIF4 CTEIF4 CDMEIF4
w w w
RM0033
17 16
CFEIF2
Reserved
w
1 0
CFEIF0
Reserved
w
17 16
CFEIF6
Reserved
w
1 0
CFEIF4
Reserved
w