Error Management - ST STM32F410 Reference Manual

Direct memory access controller (DMA)
8.3.19

Error management

The DMA controller can detect the following errors:
•
Transfer error: the transfer error interrupt flag (TEIFx) is set when:
–
–
•
FIFO error: the FIFO error interrupt flag (FEIFx) is set if:
–
–
–
•
Direct mode error: the direct mode error interrupt flag (DMEIFx) can only be set in the
peripheral-to-memory mode while operating in direct mode and when the MINC bit in
the DMA_SxCR register is cleared. This flag is set when a DMA request occurs while
the previous data have not yet been fully transferred into the memory (because the
memory bus was not granted). In this case, the flag indicates that 2 data items were be
transferred successively to the same destination address, which could be an issue if
the destination is not able to manage this situation
In direct mode, the FIFO error flag can also be set under the following conditions:
• In the peripheral-to-memory mode, the FIFO can be saturated (overrun) if the memory
bus is not granted for several peripheral requests.
•
In the memory-to-peripheral mode, an underrun condition may occur if the memory bus
has not been granted before a peripheral request occurs.
If the TEIFx or the FEIFx flag is set due to incompatibility between burst size and FIFO
threshold level, the faulty stream is automatically disabled through a hardware clear of its
EN bit in the corresponding stream configuration register (DMA_SxCR).
If the DMEIFx or the FEIFx flag is set due to an overrun or underrun condition, the faulty
stream is not automatically disabled and it is up to the software to disable or not the stream
by resetting the EN bit in the DMA_SxCR register. This is because there is no data loss
when this kind of errors occur.
When the stream's error interrupt flag (TEIF, FEIF, DMEIF) in the DMA_LISR or DMA_HISR
register is set, an interrupt is generated if the corresponding interrupt enable bit (TEIE,
FEIE, DMIE) in the DMA_SxCR or DMA_SxFCR register is set.
Note: When a FIFO overrun or underrun condition occurs, the data is not lost because the
peripheral request is not acknowledged by the stream until the overrun or underrun
condition is cleared. If this acknowledge takes too much time, the peripheral itself may
detect an overrun or underrun condition of its internal buffer and data might be lost.
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a bus error occurs during a DMA read or a write access
a write access is requested by software on a memory address register in
double-buffer mode whereas the stream is enabled and the current target memory
is the one impacted by the write into the memory address register (refer to
Section 8.3.10: Double-buffer
a FIFO underrun condition is detected
a FIFO overrun condition is detected (no detection in memory-to-memory mode
because requests and transfers are internally managed by the DMA)
the stream is enabled while the FIFO threshold level is not compatible with the
size of the memory burst (refer to
mode)
Table 35: FIFO threshold
RM0401 Rev 3
RM0401
configurations)