Types Of Exception Handling And Their Priority - Hitachi H8/300H Series Programming Manual

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3.2 Program Execution State
In this state the CPU executes program instructions in normal sequence.
3.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from
the exception vector table and branches to that address. In interrupt exception handling the CPU
references the stack pointer (ER7) and saves the program counter and condition-code register.

3.3.1 Types of Exception Handling and Their Priority

Exception handling is performed for resets, interrupts, and trap instructions. Table 3-1 indicates
the types of exception handling and their priority.
Table 3-1 Exception Handling Types and Priority
Priority
Type of Exception
High
Reset
Interrupt
Trap instruction
Low
Note: Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or
immediately after reset exception handling.
Figure 3-3 classifies the exception sources. For further details about exception sources, vector
numbers, and vector addresses refer to the relevant microcontroller hardware manual.
Exception sources
Detection Timing
Synchronized with
clock
End of instruction
execution (see note)
When TRAPA
instruction is executed
Reset
External interrupts
Interrupt
Internal interrupts (from on-chip supporting modules)
Trap instruction
Figure 3-3 Classification of Exception Sources
Start of Exception Handling
Exception handling starts
immediately when RES changes
from low to high
When an interrupt is requested,
exception handling starts at the end
of the current instruction or current
exception-handling sequence
Exception handling starts when a
trap (TRAPA) instruction is executed
241

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