Master Control Register (Mcr) - Hitachi H8S/2628 Hardware Manual

• HCAN Monitor Register (HCANMON)
15.3.1

Master Control Register (MCR)

MCR is an 8-bit register that controls the HCAN.
Bit Bit Name
7 MCR7

6
5 MCR5

4, 3
2 MCR2
1 MCR1
Rev. 1.0, 09/02, page 358 of 568
Initial Value R/W
0 R/W
0 R
0 R/W
All 0 R
0 R/W
0 R/W
Description
HCAN Sleep Mode Release
When this bit is set to 1, the HCAN automatically
exits HCAN sleep mode on detection of CAN bus
operation.
Reserved
This bit is always read as 0. The write value should
always be 0.
HCAN Sleep Mode
When this bit is set to 1, the HCAN transits to
HCAN sleep mode. When this bit is cleared to 0,
HCAN sleep mode is released.
Reserved
These bits are always read as 0. The write value
should always be 0.
Message Transmission Method
0: Transmission order determined by message
identifier priority
1: Transmission order determined by mailbox
(buffer) number priority (TXPR1 > TXPR15)
Halt Request
When this bit is set to 1, the HCAN transits to
HCAN HALT mode. When this bit is cleared to 0,
HCAN HALT mode is released.