Individual Memory Control Register (Mcr) - Hitachi SH7709S Hardware Manual

10.2.5

Individual Memory Control Register (MCR)

The individual memory control register (MCR) is a 16-bit readable/writable register that specifies
RAS and CAS timing for synchronous DRAM (areas 2 and 3), specifies address multiplexing, and
controls refresh. This enables direct connection of synchronous DRAM without external circuits.
MCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode. Bits TPC1–TPC0, RCD1–RCD0, TRWL1–TRWL0, TRAS1–TRAS0, RASD, and
AMX3–AMX0 are written to in the initialization after a power-on reset and should not then be
modified again. When RFSH and RMODE are written to, write the same values to the other bits.
When using synchronous DRAM, do not access areas 2 and 3 until this register is initialized.
Bit:
TPC1
Initial value:
R/W: R/W
Bit:
RASD
Initial value:
R/W: R/W
Bits 15 and 14—RAS Precharge Time (TPC1, TPC0): When synchronous DRAM interface is
selected as connected memory, they set the minimum number of cycles until output of the next
bank-active command after precharge.
Bit 15: TPC1 Bit 14: TPC0
0 0
1
1 0
1
15 14 13
TPC0 RCD1
0 0 0
R/W R/W
7 6 5
AMX3 AMX2
0 0 0
R/W R/W
Description
1 cycle
2 cycles
3 cycles
4 cycles
12 11 10
RCD0 TRWL1 TRWL0
0 0 0
R/W R/W R/W
4 3 2
AMX1 AMX0 RFSH
0 0 0
R/W R/W R/W
9 8
TRAS1 TRAS0
0 0
R/W R/W
1 0
—
RMODE
0 0
R/W R
(Initial value)
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