Break Address Register B (Barb); Break Control Register A (Bcra) - Hitachi H8S/2628 Hardware Manual

6.2.2

Break Address Register B (BARB)

BARB is the channel B break address register. The bit configuration is the same as for BARA.
6.2.3

Break Control Register A (BCRA)

BCRA controls channel A PC breaks. BCRA also contains a condition match flag.
Bit Bit Name Initial Value
7 CMFA 0
6 CDA 0
5 BAMRA2 0
4 BAMRA1 0
3 BAMRA0 0
2 CSELA1 0
1 CSELA0 0
0 BIEA 0
R/W Description
R/W Condition Match Flag A
[Setting condition]
When a condition set for channel A is satisfied
[Clearing condition]
When 0 is written to CMFA after reading CMFA = 1
R/W CPU Cycle/DTC Cycle Select A
Selects the channel A break condition bus master.
0: CPU
1: CPU or DTC
R/W Break Address Mask Register A2 to A0
R/W
These bits specify which bits of the break address set
R/W
in BARA are to be masked.
000: BAA23 to BAA0 (All bits are unmasked)
001: BAA23 to BAA1 (Lowest bit is masked)
010: BAA23 to BAA2 (Lower 2 bits are masked)
011: BAA23 to BAA3 (Lower 3 bits are masked)
100: BAA23 to BAA4 (Lower 4 bits are masked)
101: BAA23 to BAA8 (Lower 8 bits are masked)
110: BAA23 to BAA12 (Lower 12 bits are masked)
111: BAA23 to BAA16 (Lower 16 bits are masked)
R/W Break Condition Select A
R/W
Selects break condition of channel A.
00: Instruction fetch is used as break condition
01: Data read cycle is used as break condition
10: Data write cycle is used as break condition
11: Data read/write cycle is used as break condition
R/W Break Interrupt Enable A
When this bit is 1, the PC break interrupt request of
channel A is enabled.
Rev. 1.0, 09/02, page 87 of 568