NXP Semiconductors S32K1 Series Hardware Design Manuallines
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NXP Semiconductors S32K1 Series Hardware Design Manuallines

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AN5426
Hardware Design Guidelines for S32K1xx Microcontrollers
Rev. 3 - December 2018

1 Introduction

The S32K series further extends the highly scalable portfolio of ARM
®
Cortex
MCUs in the automotive industry. It builds on the legacy of the KEA
series, whilst introducing higher memory options alongside a richer peripheral
set extending capability into a variety of automotive applications.
With a 2.70-5.5 V supply and focus on automotive environment robustness,
the S32K series devices are well suited to a wide range of applications in
electrical harsh environments. These devices are optimized for cost-sensitive
applications offering low pin-count options.
The S32K series offers a broad range of memory, peripherals, and package
options. They share common peripherals and pin counts allowing developers
to migrate easily within the MCU family or among the MCU families to take
advantage of more memory or feature integration. This scalability allows
developers to standardize on the S32K series for their end product platforms,
maximizing hardware and software reuse and reducing timeto-market.
Following are the general features of the S32K series MCUs:
• 32-bit ARM Cortex-M4 core with IEEE-754 compliant FPU, executing up
to 112 MHz
• Scalable memory footprints up to 2 MB flash and up to 256 KB SRAM
• Precision mixed-signal capability with on chip analog comparators and
multiple 12-bit ADCs
• Powerful timers for a broad range of applications including motor control,
lighting control and body applications
• Serial communication interfaces such as LPUART, LPSPI, LPI2C,
FlexCAN, CAN-FD, FlexIO and so on.
• SHE specification compliant security module
• Single power supply (2.70-5.5 V) with full functional flash program/
erase/read operations
• Functional safety compliance with ISO26262, with internal watchdog,
voltage monitors, clock monitors, memory protection and ECC
• Ambient operation temperature range: -40 °C to 125°C
• Software enablement: S32 Software Development Kit (SDK), S32 Design Studio (S32DS)

2 S32K family comparison

Please refer to the latest version of the Reference Manual for details.
Contents
1 Introduction.......................................... 1
®
2 S32K family comparison..................... 1
3 Power supplies.................................... 2
4 Clock circuitry......................................3
5.2 RESET system...................... 11
7 Communication modules.................. 13
9 Unused pins....................................... 26
10.2 Grounding .......................... 27
11 PCB layer stacking...........................30
12 Injection current...............................31
13 References........................................31
14 Revision history............................... 31
Application Note
capacitors ............................... 3
module...................................13
module...................................17

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  • Page 1: Table Of Contents

    AN5426 Hardware Design Guidelines for S32K1xx Microcontrollers Rev. 3 — December 2018 Application Note Contents 1 Introduction 1 Introduction.......... 1 ® The S32K series further extends the highly scalable portfolio of ARM 2 S32K family comparison..... 1 ® Cortex MCUs in the automotive industry. It builds on the legacy of the KEA 3 Power supplies........

  • Page 2: Power Supplies

    NXP Semiconductors Power supplies 3 Power supplies The power and ground pins are described in subsequent sections. Figure 1. Power supply pins Table 1. Power domains and decoupling capacitors Power Descripti Voltage Characte Bulk/Bypass Capacitor for domain Decoupli Domain ristics...

  • Page 3: Bulk And Decoupling Capacitors

    NXP Semiconductors Clock circuitry Table 1. Power domains and decoupling capacitors (continued) VSSA Analog Ground VREFL reference voltage 1. VDD and VDDA must be shorted to a common reference on PCB. Appropriate decoupling capacitors to be used to filter noise on the supplies 3.1 Bulk and decoupling capacitors...

  • Page 4: Suggestions For The Pcb Layout Of Oscillator Circuit

    NXP Semiconductors Clock circuitry Figure 2. Reference oscillator circuit Table 2. Components of the oscillator circuit Symbol Description Bias Resistor Feedback Resistor • When Low-gain is selected, internal RF will be selected, and external RF is not required. • When High-gain is selected, external RF(1M Ohm) need to be connected for proper operation of crystal.

  • Page 5: Debug And Programing Interface

    NXP Semiconductors Debug and programing interface • It is recommended to send the PCB to the crystal manufacturer to determine the negative oscillation margin as well as the optimum regarding C and C capacitors. The data sheet includes recommendations for the tank capacitors C...

  • Page 6: Debug Connector Pinouts

    NXP Semiconductors Debug and programing interface Table 3. JTAG signal description JTAG Mode SWD Mode Signal SWCLK Clock into the core JTAG Test Data Input JTAG Test Data Output / SWV trace data output (SWO) SWDIO JTAG Test Mode Select / SWD data in/out The pull up/down resitors for the JTAG signals are included internally by the default pad configuration.
  • Page 7 NXP Semiconductors Debug and programing interface Figure 4. 20-pin Cortex Debug D ETM connector pin layout 5.1.2 10-pin Cortex Debug connector For device without ETM, you can use an even smaller 0.05” 10-pin connector (Samtec FTSH-105) for debug. Similar to the 20- pin Cortex Debug D ETM connector, both JTAG and Serial-Wire debug protocols are supported in the 10-pin version.
  • Page 8 NXP Semiconductors Debug and programing interface Figure 5. 10-pin Cortex Debug connector pin layout 5.1.3 Legacy 20-pin IDC connector A common debug connector used in ARM development boards is the 20-pin IDC connector. The 20-pin IDC connector arrange support JTAG debug, Serial Wire debug (SWIO and SWCLK), Serial Wire Output (SWO). The nICEDETECT pin allows the target system to detect if a debugger is connected.
  • Page 9 NXP Semiconductors Debug and programing interface Figure 6. 20-pin IDC connector 5.1.4 38-pin Mictor connector In some ARM system designs, Mictor connector is used when trace port is required (example, for instruction trace with ETM). It can also be used for JTAG/SWD connection. The 20-pin IDC connector can be connected in parallel with the Mictor connector (only one is use at a time).
  • Page 10 NXP Semiconductors Debug and programing interface Figure 7. 38-pin Mictor connector Typically a Cortex-M3 or Cortex-M4 microcontroller only has 4-bit of trace data signals, so most of the trace data pins on the Mictor connectors are not used. The Mictor connector is used mostly in other ARM Cortex processors (CortexA8/A9, Cortex-R4) or in some multiprocessor systems the trace system might require a wider trace port.

  • Page 11: Reset System

    NXP Semiconductors Analog comparator interface 5.2 RESET system Resetting the MCU provides a way to start processing from a known set of initial conditions. System reset begins with the on-chip regulator in full regulation and system clocking generation from an internal reference.
  • Page 12 NXP Semiconductors Analog comparator interface Figure 8. General windowed timing diagram Figure 9. CMP high level diagram The switching of the high-speed interfaces or any GPIO may introduce some noise to the analog or comparator inputs due to inductance/capacitive coupling between the MCU pins. The cross-talk may be introduced by PCB tracks that run close to each Hardware Design Guidelines for S32K1xx Microcontrollers , Rev.

  • Page 13: Communication Modules

    NXP Semiconductors Communication modules other or that cross each other. In order to avoid and mitigate the high-frequency noise and any coupling. Please ensure that the analog comparator input signal impedance is 50K or less.(see Figure 9. on page 12) Figure 10.
  • Page 14 NXP Semiconductors Communication modules • Interrupt, DMA or polled operation: — Transmit data register empty and transmission complete — Receive data register full — Receive overrun, parity error, framing error, and noise error — Idle receiver detect — Active edge on receive pin —...
  • Page 15 NXP Semiconductors Communication modules The LIN bus topology utilizes a single master and multiple nodes, as shown below. Connecting application modules to the vehicle network makes them accessible for diagnostics and service. Figure 11. LIN bus topology The LIN transmitter is a low-side MOSFET with current limitation and overcurrent transmitter shutdown. A selectable internal pull- up resistor with a serial diode structure is integrated, so no external pull-up components are required for the application in a slave node.
  • Page 16 NXP Semiconductors Communication modules 7.1.1 LIN components data Table 5. LIN components Reference Part Mounting Remark DMLIN Diode Mandatory only for master Reverse Polarity protection from LIN to VSUP. RML1 and RML2 Mandatory only for Master Resistor: 2 kΩ For Master ECU...

  • Page 17: Can Interface For Flexcan Module

    NXP Semiconductors Communication modules 7.2 CAN interface for FlexCAN module The physical layer characteristics for CAN are specified in ISO-11898-2. This standard specifies the use of cable comprising parallel wires with an impedance of nominally 120 Ω (95 Ω as minimum and 140 Ω as maximum). The use of shielded twisted pair cables is generally necessary for electromagnetic compatibility (EMC) reasons, although ISO-11898-2 also allows for unshielded cable.
  • Page 18 NXP Semiconductors Communication modules Figure 14. CAN physical transceiver circuit Figure 15. CAN physical transceiver circuit with common mode choke Hardware Design Guidelines for S32K1xx Microcontrollers , Rev. 3, December 2018 Application Note 18 / 33...
  • Page 19 NXP Semiconductors Communication modules 7.2.1 CAN components data Table 6. CAN components Reference Description Denotes a guard track next to a high/medium speed track. Guard tracks are connected such that each end of the track is connected to ground. A guard track should be connected to the ground plane at least every 500 mils.

  • Page 20: Inter-Integrated Circuit Iic

    NXP Semiconductors Communication modules 7.2.2.1 Parallel termination In CAN applications, both ends of the bus must be terminated because any node on the bus may transmit/receive data. Each end of the link has a termination resistor equal to the characteristic impedance of the cable, although the recommended value for the termination resistors is nominally 120 Ω...
  • Page 21 NXP Semiconductors Communication modules for further expansion and system development. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull-up resistor (see Figure 18. on page 21. When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open collector in order to perform the wired-AND function.

  • Page 22: Ethernet Mac Interface

    NXP Semiconductors Communication modules Figure 19. Maximum value of RP as a function of bus capacitance for a standard-mode I2C-bus 7.4 Ethernet MAC Interface MII/RMII Interface signal can be directly routed to the MAC-NET interface, however series termination resistors may be considerate on RXCLK, TXCLK and all RX/TX signals for EMI suppression.

  • Page 23: Quad Serial Peripheral Interface

    NXP Semiconductors Quad Serial Peripheral Interface external crystal running at a nominal 25 MHz or from the CLK_OUT signal on the switch. When the Ethernet Switch is configured for MAC-MAC communication, the switch provides the clocks and acts like a PHY.
  • Page 24 NXP Semiconductors Quad Serial Peripheral Interface Figure 22. External memory option - Single Quad Flash on the A-side • Single HyperRAM on the B-side Figure 23. External memory option - Single HyperRAM on the B-side • Single Quad Flash on the B-side.
  • Page 25 NXP Semiconductors Quad Serial Peripheral Interface Figure 24. External memory option - Single Quad Flash on the B-side Data and Clock Signal Termination: Clock generation and distribution becomes more difficult as the speed and performance of microprocessors increase to higher limits. Controlled and precise clocking distribution techniques are needed to maintain a synchronous system.

  • Page 26: Unused Pins

    NXP Semiconductors Unused pins signal integrity, avoid using multiple signal layers for data signal routing. All signal traces should have a continuous and solid reference plane, either GND or VDD. Clock Signal Routing: In high speed synchronous data transfer, good signal integrity in a PCB design is of critical importance, especially for the clock signals, SCLK and DQS.

  • Page 27: General Board Layout Guidelines

    NXP Semiconductors General board layout guidelines 10 General board layout guidelines 10.1 Traces recommendations A right angle in a trace can cause more radiation. The capacitance increases in the region of the corner and the characteristic impedance changes. This impedance change causes reflections. Avoid right-angle bends in a trace and try to route them with at least two 45°...

  • Page 28: Emi/Emc And Esd Considerations For Layout

    NXP Semiconductors General board layout guidelines Figure 28. Eliminating floating metal/shape 10.3 EMI/EMC and ESD considerations for layout These considerations are important for all system and board designs. Though the theory behind this is well explained, each board and system experiences this in its own way. There are many PCB and component related variables involved.
  • Page 29 NXP Semiconductors General board layout guidelines Figure 29. Electromagnetic noise propagation The design considerations narrow down to: • The radiated & conducted EMI from the board should be lower than the allowed levels by the standards you are following. • The ability of the board to operate successfully counteracting the radiated & conducted electromagnetic energy (EMC) from other systems around it.

  • Page 30: Pcb Layer Stacking

    NXP Semiconductors PCB layer stacking 11 PCB layer stacking To reach signal integrity and performance requirements, at minimum a four-layer PCB is recommended for implementing Ethernet applications and systems. The following layer stack-ups are recommended for four, six, and eight-layer boards, although other options are possible.

  • Page 31: Injection Current

    Crystal Oscillator Troubleshooting Guide - NXP Semiconductors • AN2049 Some Characteristics and Design Notes for Crystal Feedback ... • AN10853 ESD and EMC sensitivity of IC - NXP Semiconductors • AN2321: Designing for Board Level Electromagnetic Compatibility - NXP Semiconductors •...
  • Page 32 NXP Semiconductors Revision history Table 7. Sample revision history (continued) Revision number Date Substantive changes 06/2017 1. In Table 1. Power domains and decoupling capacitors on page 2 Footnote is added in the table 2. In Clock circuitry on page 3 the value of Fast...
  • Page 33 How To Reach Us Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to Home Page: design or fabricate any integrated circuits based on the information in this document. NXP nxp.com reserves the right to make changes without further notice to any products herein.

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