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LPC5410x User manual

Rev. 2.4 — 13 September 2016

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Page 1 UM10850 LPC5410x User manual Rev. 2.4 — 13 September 2016 User manual Document information Info Content Keywords LPC5410x, ARM Cortex-M4, ARM Cortex-M0+, microcontroller, sensor Abstract LPC5410x User Manual...
Page 2 Section 4.5.50 “Device ID1 register”. • Removed IrDA mode from Section 21.5 “General description” Chapter 21 “LPC5410x USARTs (USART0/1/2/3)”. • Updated Table 307 “USART Configuration register (CFG, offset 0x00) bit description”. Removed IOMODE from the table. •...
Page 3 CPU via this register if needed after it is brought out of reset by Cortex-M4. • Added text to Section 4.6.3 “Brown-out detection”: On the LPC5410x, the BOD is enabled by default after power-up. At this time the BOD is set to the lowest value (1.5v) with no factory trimming applied.
Page 4 Table 340 “Register overview: I2C0/1/2 (register base addresses 0x4009 4000 (I2C0), 0x4009 8000 (I2C1), 0x4009 C000 (I2C2))”. • Added the Flash Management Registers FMSSTART and FMSSTOPUpdated to Chapter 28 “LPC5410x Flash signature generator”. • Typographic errors have been corrected and minor pieces of information added or clarified throughout the document.
Page 5: Introduction
NXP Semiconductors LPC5410x User manual Revision history …continued Date Description 20141104 Initial release of the LPC5410x User Manual Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com UM10850 All information provided in this document is subject to legal disclaimers.
Page 6: Chapter 1: Lpc5410X Introductory Information
32-bit core which is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0+ coprocessor offers up to 100 MHz performance with a simple instruction set and reduced code size. Refer to LPC5410x data sheets for complete details on specific products and configurations. 1.2 Features •...
Page 7 UM10850 NXP Semiconductors Chapter 1: LPC5410x Introductory information – Non-maskable Interrupt (NMI) with a selection of sources. – Serial Wire Debug (SWD) with 4 breakpoints and 2 watchpoints. – System tick timer. • On-Chip memory: – Up to 512 KB on-chip flash programming memory with flash accelerator and 256 Byte page write and erase.
Page 8: Block Diagram
UM10850 NXP Semiconductors Chapter 1: LPC5410x Introductory information – 32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power domain. A timer in the RTC can be used for wake-up from all low power modes including Deep power-down, with 1 ms resolution.
Page 9: Architectural Overview
UM10850 NXP Semiconductors Chapter 1: LPC5410x Introductory information 1.3 Block diagram Grey-shaded blocks show peripherals provide DMA request lines or that can provide hardware triggers for DMA transfers. Fig 1. Block diagram UM10850 All information provided in this document is subject to legal disclaimers.
Page 10: General Description
UM10850 NXP Semiconductors Chapter 1: LPC5410x Introductory information 1.4 Architectural overview The ARM Cortex-M4 includes three AHB-Lite buses, one system bus and the I-code and D-code buses. One bus is dedicated for instruction fetch (I-code), and one bus is dedicated for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices.
Page 11: Chapter 2: Lpc5410X Memory Mapping
2.1.1.2 SRAM usage notes Although always contiguous on all LPC5410x devices, SRAM0 and SRAM1 are placed on different AHB matrix ports. This allows user programs to potentially obtain better performance by dividing RAM usage among the 2 ports. For example, simultaneous access to SRAM0 by the CPU and SRAM1 by the system DMA controller does not result in any bus stalls for either master.
Page 12: Memory Mapping
UM10850 NXP Semiconductors Chapter 2: LPC5410x Memory mapping Generally speaking, the CPU will read or write all peripheral data at some point, even when all such data is read from or sent to a peripheral by DMA. So, minimizing stalls is likely to involve putting data to/from different peripherals in RAM on each port.
Page 13: Ahb Multilayer Matrix
UM10850 NXP Semiconductors Chapter 2: LPC5410x Memory mapping 2.1.2 Memory mapping The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers. Fig 2. Memory mapping UM10850 All information provided in this document is subject to legal disclaimers.
Page 14: How To Read This Chapter
Chapter 2: LPC5410x Memory mapping 2.1.3 AHB multilayer matrix The LPC5410x uses a multi-layer AHB matrix to connect the CPU buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slave ports of the matrix to be accessed simultaneously by different bus masters.
Page 15: Chapter 3: Lpc5410X Nested Vectored Interrupt Controller (Nvic)
(NVIC) Rev. 2.4 — 13 September 2016 User manual 3.1 How to read this chapter Available interrupt sources may vary with specific LPC5410x device type. 3.2 Features • Nested Vectored Interrupt Controller that is an integral part of each CPU.
Page 16 UM10850 NXP Semiconductors Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC) Table 2. Connection of interrupt sources to the NVIC Interrupt Name Description Flags GINT0 GPIO group 0 interrupt Enabled pin interrupts PIN_INT0 Pin interrupt 0 or pattern match engine slice 0 int...
Page 17 UM10850 NXP Semiconductors Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC) 3.4 Register description The NVIC registers are located on the ARM private peripheral bus. Table 3. Register overview: NVIC (base address 0xE000 E000) Name Access Address Description Reset Refer-...
Page 18: Interrupt Set-Enable Register 0 Register
UM10850 NXP Semiconductors Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC) 3.4.1 Interrupt Set-Enable Register 0 register The ISER0 register allows enabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. The remaining interrupts are enabled via the ISER1...
Page 19: Interrupt Set-Enable Register 1 Register
UM10850 NXP Semiconductors Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC) 3.4.2 Interrupt Set-Enable Register 1 register The ISER1 register allows enabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. Disabling interrupts is done through the ICER0 and ICER1 registers (Section 3.4.3...
Page 20: Interrupt Set-Pending Register 1 Register
UM10850 NXP Semiconductors Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC) Section 3.4.8). Table 8. Interrupt Set-Pending Register 0 register Name Function 31:0 ISP_... Peripheral interrupt pending set. Bit numbers match ISER0 registers (Table 4). Unused bits are reserved. Write: writing 0 has no effect, writing 1 changes the interrupt state to pending.
Page 21: Interrupt Active Bit Register 0
UM10850 NXP Semiconductors Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC) 3.4.9 Interrupt Active Bit Register 0 The IABR0 register is a read-only register that allows reading the active state of the first 32 peripheral interrupts. Bits in IABR are set while the corresponding interrupt service routines are in progress.
Page 22: Interrupt Priority Register 2
UM10850 NXP Semiconductors Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC) Table 15. Interrupt Priority Register 1 …continued Name Function 15:13 IP_PINT0 Pin interrupt / pattern match engine slice 0 priority. 0 = highest priority. 31 (0x1F) = lowest priority.
Page 23: Interrupt Priority Register 5
UM10850 NXP Semiconductors Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC) Table 18. Interrupt Priority Register 4 Name Function Unused IP_SCT0 SCT0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 Unused 15:13 IP_USART0 USART 0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority.
Page 24: Interrupt Priority Register 8
UM10850 NXP Semiconductors Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC) Table 21. Interrupt Priority Register 7 Name Function Unused IP_ADC0THOV ADC 0 threshold and error interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 12:8 Unused 15:13 IP_RTC Real Time clock (RTC) interrupt priority.
Page 25: Software Trigger Interrupt Register
UM10850 NXP Semiconductors Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC) Table 24. Interrupt Priority Register 10 Name Function Unused IP_RIT Repetitive interrupt Timer interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 31:8 Reserved 3.4.22 Software Trigger Interrupt Register The STIR register provides an alternate way for software to generate an interrupt, in addition to using the ISPR registers.
Page 26: Chapter 4: Lpc5410X System Configuration (Syscon)
UM10850 Chapter 4: LPC5410x System configuration (SYSCON) Rev. 2.4 — 13 September 2016 User manual 4.1 Features • System and bus configuration. • Clock select and control. • PLL configuration • Reset control. • Wake-up control. • BOD configuration. •...
Page 27: Measure The Frequency Of A Clock Signal
UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) – The RTC 32 kHz oscillator Section 4.5.16 “Main clock source select register A” Section 4.5.17 “Main clock source select register B”. 2. Select the divider value for the system clock. A divider value of 0 disables the system clock.
Page 28 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) The low-power watchdog oscillator provides a fixed clock of approximately 500 kHz. The accuracy of this clock is limited to +/- 40% over temperature, voltage, and silicon processing variations. To determine the actual watchdog oscillator output, use the frequency measure block.
Page 29: Register Description
UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5 Register description All system control block registers reside on word address boundaries. Details of the registers appear in the description of each function. System configuration functions are divided into 3 groups: Main system configuration at base address 0x4000 0000 (see...
Page 30 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Table 27. Register overview: Main system configuration (base address 0x4000 0000) …continued Name Access Offset Description Reset value Reference CLKOUTDIV 0x10C CLKOUT clock divider Table 60 FREQMECTRL 0x120 Frequency measure register...
Page 31: Ahb Matrix Priority Register
UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Table 28. Register overview: Asynchronous system configuration (base address 0x4008 0000) …continued Name Access Offset Description Reset value Reference ASYNCAPBCLKCTRLCLR 0x018 Clear bits in ASYNCAPBCLKCTRL Table 95 ASYNCAPBCLKSELA 0x020 Async APB clock source select A...
Page 32: Nmi Source Selection Register
UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Table 31. System tick timer calibration register (SYSTCKCAL, address 0x4000 0014) bit description Symbol Description Reset value 23:0 System tick timer calibration value. SKEW Initial value for the Systick timer. NOREF Initial value for the Systick timer.
Page 33: System Reset Status Register
UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.5 System reset status register The SYSRSTSTAT register shows the source of the latest reset event. The bits are cleared by writing a one to any of the bits. The POR event clears all other bits in this register.
Page 34: Peripheral Reset Control Register 1
UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Table 35. Peripheral reset control register 0 (PRESETCTRL0, address 0x4000 0044) bit description Symbol Description Reset value GPIO0_RST GPIO0 reset control. 0 = Clear reset to this function. 1 = Assert reset to this function.
Page 35: Peripheral Reset Control Set Register 0
UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Table 36. Peripheral reset control register 1 (PRESETCTRL1, address 0x4000 0048) bit description Symbol Description Reset value 21:11 Reserved. Read value is undefined, only zero should be written. CT32B2_RST CT32B2 reset control.
Page 36: Peripheral Reset Control Clear Register 1
UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.11 Peripheral reset control clear register 1 Writing a 1 to a bit position in PRESETCTRLCLR1 clears the corresponding position in PRESETCTRL1. This is a write-only register. For bit assignments, see Table Table 40.
Page 37: Main Clock Source Select Register A
UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.16 Main clock source select register A This register selects one of the internal oscillators, IRC, system oscillator, or watchdog oscillator. The oscillator selected is then one of the inputs to the main clock source select...
Page 38: Clkout Clock Source Select Register A
UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Remark: Note that this selection is internally synchronized: the clock being switched from and the clock being switched to must both be running and have occurred in specific states before the selection actually changes.
Page 39: System Pll Clock Source Select Register
UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Table 49. CLKOUT clock source select register (CLKOUTSELB, address 0x4000 0098) bit description Symbol Value Description Reset value CLKOUT clock source CLKOUTSELA. Clock source selected in the CLKOUTSELA register. reserved reserved...
Page 40: Ahb Clock Control Register 0
UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.22 AHB Clock Control register 0 The AHBCLKCTRL0 register enables the clocks to individual system and peripheral blocks. The system clock (bit 0) provides the clock for the AHB, the APB bridge, the CPU, the SYSCON block, and the PMU.
Page 41: Ahb Clock Control Register 1
UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.23 AHB Clock Control register 1 The AHBCLKCTRL1 register enables the clocks to individual peripheral blocks. Table 52. AHB Clock Control register 1 (AHBCLKCTRL1, address 0x4000 00C4) bit description Symbol Description Reset value Enables the clock for the Multi-Rate Timer.
Page 42: Ahb Clock Control Clear Register 1
UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Table 55. Clock control clear register 0 (AHBCLKCTRLCLR0, address 0x4000 00D0) bit description Symbol Description Reset value 31:0 CLK_CLR0 Writing ones to this register clears the corresponding bit or bits in the AHBCLKCTRL0 register, if they are implemented.
Page 43: Clkout Clock Divider Register
UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Table 59. ADC clock source divider (ADCCLKDIV, address 0x4000 0108) bit description Symbol Description Reset value ADC clock divider value. 0: Disable ADC clock. 1: Divide by 1. 255: Divide by 255.
Page 44: Flash Configuration Register
UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.33 Flash configuration register Depending on the system clock frequency, access to the flash memory can be configured with various access times by writing to the FLASHCFG register. It is recommended to use...
Page 45: Fifo Control Register
UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Table 62. Flash configuration register (FLASHCFG, main syscon: address 0x4000 0124) bit description Symbol Value Description Reset value 11:7 Reserved 15:12 FLASHTIM Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1.
Page 46: Irc Control Register
UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.35 IRC control register This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset and written by the boot code on start-up. Table 64. IRC control register (IRCCTRL, address 0x4000 0184) bit description...
Page 47 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.37 PLL registers The PLL provides a wide range of frequencies and can potentially be used for many on-chip functions. the PLL can be used with or without a spread spectrum clock generator.
Page 48 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.37.2 System PLL status register The read-only PLL0_STAT SYSPLLSTAT register provides the PLL lock status Remark: The lock status does not reliably indicate the PLL status for the following two configurations: spread-spectrum mode or fractional enabled or low input clock frequencies such as 32 kHz.
Page 49 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.37.4 System PLL P-divider register Remark: The PLL P-divider register does not use the direct binary representation of P divide value directly. Instead, it uses an encoded version PDEC. Remark: While the PLL0 output is in use, do not change the PDEC value. Changing the PDEC value changes the PLL output frequency and can cause the system to fail.
Page 50 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.37.5.1 System PLL spread spectrum control register 0 Table 70. System PLL spread spectrum control register 0 (SYSPLLSSCTRL0, address 0x4000 01C0) bit description Symbol Value Description Reset value 16:0 MDEC Decoded M-divider coefficient value MREQ MDEC reload request.
Page 51 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) else if (M >=60) then SELI = 4*(1024/(M+9)) else SELI = (M & 0x3C) + 4; /* & denotes bitwise AND */ SELR = 0; Remark: If the 32 kHz RTC oscillator is used as the reference input to the PLL, then use fixed values SELI=1, SELP=6, and SELR=0, instead of applying the above rules.
Page 52 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Table 71. System PLL spread spectrum control register 1 (SYSPLLSSCTRL1, address 0x4000 01C4) bit description Symbol Value Description Reset value 27:26 Modulation waveform control 0 = no compensation Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum.
Page 53 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.38 Power Configuration register The PDRUNCFG register controls the power to the various analog blocks. Remark: for safety, this register should not be written. Changing the contents of PDRUNCFG should be accomplished by writing to PDRUNCFGSET and/or PDRUNCFGCLR.
Page 54 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Table 73. Power configuration set register (PDRUNCFGSET, address 0x4000 0214) bit description Symbol Description Reset value 31:0 PD_SET Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG register, if they are implemented.
Page 55 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.41 Start enable register 0 The STARTER0 and STARTER1 registers enable an interrupt for wake-up from deep-sleep and power-down modes. Some interrupts are typically used in sleep mode only and will not occur during deep-sleep or power-down modes because relevant clocks are stopped.
Page 56 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Table 75. Start enable register 0 (STARTER0, address 0x4000 0240) bit description …continued Symbol Description Reset value CT32B4 Standard counter/timer CT32B4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled.Typically used in sleep mode only since the peripheral clock must be running for it to function.
Page 57 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Table 76. Start enable register 1 (STARTER1, address 0x4000 0244) bit description Symbol Description Reset value GINT1 Group interrupt 0 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. PINT4 GPIO pin interrupt 4 wake-up. 0 = Wake-up disabled. 1 = Wake-up enabled. Not for pattern match.
Page 58 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Table 79. Start enable clear register 0 (STARTERCLR0, address 0x4000 0250) bit description Symbol Description Reset value 31:0 START_CLR0 Writing ones to this register clears the corresponding bit or bits in the STARTER0 register, if they are implemented.
Page 59 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.47 Dual-CPU related registers These registers control usage aspects of the two CPUs in an LPC54102 device. They are not used in an LPC54101 device that only provide a single CPU.
Page 60 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.47.2 Coprocessor Boot register CPBOOT can be used in an application that uses both CPUs in order to send the slave processor (the CPU not selected as the master by the MASTERCPU bit in the CPUCTRL register) to an appropriate boot address that is different than the master CPU.
Page 61 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.48 JTAG ID code register This register contains the JTAG ID code. Table 85. JTAG ID code register (JTAGIDCODE, address 0x4000 03F4) bit description Symbol Description Value 31:0 JTAGID JTAG ID code.
Page 62 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.51 Asynchronous peripheral reset control register The ASYNCPRESETCTRL register allows software to reset specific peripherals attached to the async APB bridge. Writing a zero to any assigned bit in this register clears the reset and allows the specified peripheral to operate.
Page 63 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Table 92. Asynchronous peripheral reset control clear register (ASYNCPRESETCTRLCLR, address 0x4008 0008) bit description Symbol Description Reset value 31:0 ARST_CLR Writing ones to this register clears the corresponding bit or bits in the ASYNCPRESETCTRL register, if they are implemented.
Page 64 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.56 Asynchronous APB clock control clear register Writing a 1 to a bit position in ASYNCAPBCLKCTRLCLR clears the corresponding position in ASYNCAPBCLKCTRL. This is a write-only register. For bit assignments, see Table Table 95.
Page 65 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Table 97. Asynchronous clock source select register B (ASYNCAPBCLKSELB, address 0x4008 0024) bit description Symbol Value Description Reset value Clock source for asynchronous clock source selector B. Main clock CLKIN System PLL output.
Page 66 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.5.61 BOD control register The BOD control register selects four separate threshold values for sending a BOD interrupt to the NVIC and for forced reset. Reset and interrupt threshold values listed in Table 100 are typical values.
Page 67 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Assertion of the POR or the BOD reset, once the operating voltage attains a usable level, starts the IRC. After the IRC-start-up time (maximum of 6 s on power-up), the IRC provides a stable clock output.
Page 68 If the BOD reset is enabled, the forced BOD reset can wake-up the chip from reduced power modes, not including deep power-down. On the LPC5410x, the BOD is enabled by default after power-up. At this time the BOD is set to the lowest value (1.5v) with no factory trimming applied. In the BOD block the interrupt portion is turned off and only the reset portion is on.
Page 69 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 4.6.4.1 PLL Features • Input frequency: Limited to on-chip sources, including the 32 kHz RTC clock and 12 MHz IRC, or up to 24 MHz from the CLKIN pin. • CCO frequency: 75 MHz to 150 MHz.
Page 70 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) The PLL lock indicator is not dependable when Fref is below 100 kHz or above 20 MHz. In fractional mode and spread spectrum mode, the PLL will generally not lock, software should use a time interval to insure the PLL will be stable.
Page 71 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 75 MHz ≤ Fcco ≤ 150 MHz • • 4 kHz ≤ Fin / N ≤ 24 MHz Normal mode with optional pre-divide In the equations, use N = 1 when the pre-divider is not used:...
Page 72 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Fig 6. PLL block diagram showing spread spectrum and fractional divide operation 4.6.4.3.3 Spread Spectrum mode The spread spectrum mode allows the PLL to change frequency automatically in a programmable manner.
Page 73 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) Table 102. System PLL status register (SYSPLLSTAT, address 0x4000 01B4) bit description Register Description Reference SYSPLLPDEC PLL P divider Section 4.5.37.4 SYSPLLSSCTRL0 PLL spread spectrum control 0 Section 4.5.37.5.1 SYSPLLSSCTRL1 PLL spread spectrum control 1 Section 4.5.37.5.2...
Page 74 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) 1. Make sure that the PLL output is disconnected from any downstream functions. If the PLL was previously being used to clock the CPU, and the CPU Clock Divider is being used, it may be set to speed up operation while the PLL is disconnected.
Page 75 UM10850 NXP Semiconductors Chapter 4: LPC5410x System configuration (SYSCON) The frequency measurement function circuit is able to measure the target frequency with an error of less than 0.1%, provided the reference frequency is precisely known. Uncertainty in the reference clock (for example the +/- 1% accuracy of the IRC) will add to the measurement error of the target clock.
Page 76 User manual 5.1 Introduction This chapter provides an overview of power related information about LPC5410x devices. These devices include a variety of adjustable regulators, power switches, and clock switches to allow fine tuning power usage to match requirements at different performance levels and reduced power modes.
Page 77 UM10850 NXP Semiconductors Chapter 5: LPC5410x Power Management b. In Power-down mode, the flash is also powered down to conserve power at the expense of a somewhat longer wake-up time. 4. Deep power-down mode: For maximal power savings, the entire system (CPUs and all peripherals) is shut down except for the PMU and the RTC.
Page 78 UM10850 NXP Semiconductors Chapter 5: LPC5410x Power Management Table 104. Wake-up sources for reduced power modes Power mode Wake-up source Conditions Deep-sleep Pin interrupts Enable pin interrupts in NVIC and STARTER0 and/or STARTER1 registers. • BOD interrupt Enable interrupt in NVIC and STARTER0 registers.
Page 79 5.3 Functional description 5.3.1 Power management The LPC5410x support a variety of power control features. In Active mode, when the chip is running, power and clocks to selected peripherals can be optimized for power consumption. In addition, there are four special modes of processor power reduction with...
Page 80 UM10850 NXP Semiconductors Chapter 5: LPC5410x Power Management • The power API provides an easy way to optimize power consumption depending on CPU load and performance requirements. See Chapter 30 “LPC5410x Power profiles/Power control API”. 5.3.3 Sleep mode In Sleep mode, the system clock to the CPU is stopped and execution of instructions is suspended until either a reset or an interrupt occurs.
Page 81 UM10850 NXP Semiconductors Chapter 5: LPC5410x Power Management Deep-sleep mode eliminates all power used by analog peripherals and all dynamic power used by the processor itself, memory systems and related controllers, and internal buses. The processor state and registers, peripheral registers, and internal SRAM values are maintained, and the logic levels of the pins remain static.
Page 82 UM10850 NXP Semiconductors Chapter 5: LPC5410x Power Management 5.3.5 Power-down mode In Power-down mode, the system clock to the processor is disabled as in Sleep mode. All analog blocks are powered down by default but can be selected to keep running if needed for waking up the part.
Page 83 UM10850 NXP Semiconductors Chapter 5: LPC5410x Power Management • RTC alarm signal or wake-up signal. See Chapter 16. Interrupts must also be enabled in the STARTER1 register (Table 76) and in the NVIC. 5.3.6 Deep power-down mode In Deep power-down mode, power and clocks are shut off to the entire chip with the exception of the RTC.
Page 84 UM10850 Chapter 6: LPC5410x Boot process Rev. 2.4 — 13 September 2016 User manual 6.1 Features • 64 KB on-chip boot ROM • Contains the boot loader with In-System Programming (ISP) facility and the following APIs: – In-Application Programming (IAP) of flash memory –...
Page 85 UM10850 NXP Semiconductors Chapter 6: LPC5410x Boot process 6.3.1 Boot process flowchart Fig 7. Boot process flowchart UM10850 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved. User manual Rev. 2.4 — 13 September 2016...
Page 86 Rev. 2.4 — 13 September 2016 User manual 7.1 How to read this chapter The IOCON block is included on all LPC5410x parts. Registers for pins that are not available on a specific package are reserved. Table 106. Available pins and configuration registers...
Page 87 UM10850 NXP Semiconductors Chapter 7: LPC5410x I/O pin configuration (IOCON) 7.4 General description 7.4.1 Pin configuration Fig 8. Pin configuration 7.4.2 IOCON registers The IOCON registers control the functions of device pins. Each GPIO pin has a dedicated control register to select its function and characteristics. Each pin has a unique set of functional capabilities.
Page 88 UM10850 NXP Semiconductors Chapter 7: LPC5410x I/O pin configuration (IOCON) pins. If a peripheral input function is defined as coming from more than one source, the values will be logically combined, possibly resulting in incorrect peripheral operation. Therefore care should be taken to avoid this situation.
Page 89 UM10850 NXP Semiconductors Chapter 7: LPC5410x I/O pin configuration (IOCON) 7.4.2.6 Input filter Some pins include a filter that can be selectively disabled by setting the FILTEROFF bit. The filter suppresses input pulses smaller than about 10 ns. 7.4.2.7 Output slew rate The SLEW bits of digital outputs that do not need to switch state very quickly should be set to “standard”.
Page 90 UM10850 NXP Semiconductors Chapter 7: LPC5410x I/O pin configuration (IOCON) 7.5 Register description Each port pin PIOm_n has one IOCON register assigned to control the pin’s electrical characteristics. Table 107. Register overview: I/O configuration (base address 0x4001 C000) Name Access...
Page 91 UM10850 NXP Semiconductors Chapter 7: LPC5410x I/O pin configuration (IOCON) 7.5.1 Type D IOCON registers (PIO0) This IOCON table applies to port pins P0[0 to 2] and P0[4 to 22]. Other pins include ADC or I C functions that alter the contents of the related IOCON registers.
Page 92 UM10850 NXP Semiconductors Chapter 7: LPC5410x I/O pin configuration (IOCON) Table 110. Type D I/O Control registers: FUNC values and pin functions Register Value of FUNC field in IOCON register PIO0_0 PIO0_0 U0_RXD SPI0_SSELN0 CT32B0_CAP0 SCT0_OUT3 PIO0_1 PIO0_1 U0_TXD SPI0_SSELN1...
Page 93 UM10850 NXP Semiconductors Chapter 7: LPC5410x I/O pin configuration (IOCON) 7.5.2 Type I IOCON registers (PIO0) This IOCON table applies to pins P0[23 to 28]. See Table 113 for recommended setting for I2C operation. Table 111. Address map PIO0_[23:28] registers...
Page 94 UM10850 NXP Semiconductors Chapter 7: LPC5410x I/O pin configuration (IOCON) The input may be turned off by clearing DIGIMODE if it is not needed. Table 114. Type I I/O Control registers: FUNC values and pin functions Value of FUNC field in IOCON register...
Page 95 UM10850 NXP Semiconductors Chapter 7: LPC5410x I/O pin configuration (IOCON) Table 116. Type A IOCON registers(PIO0_[29:31], address offsets [0x074:0x07C]) bit description Symbol Value Description Reset value Controls open-drain mode. Normal. Normal push-pull output Open-drain. Simulated open-drain output (high drive disabled) 31:11 Reserved.
Page 96 UM10850 NXP Semiconductors Chapter 7: LPC5410x I/O pin configuration (IOCON) Table 119. Type A I/O Control registers: FUNC values and pin functions Value of FUNC field in IOCON register Register 000 PIO0_29 PIO0_29/ADC_0 SCT0_OUT2 CT32B0_MAT3 CT32B0_CAP1 CT32B0_MAT1 PIO0_30 PIO0_30/ADC_1 SCT0_OUT3...
Page 97 UM10850 NXP Semiconductors Chapter 7: LPC5410x I/O pin configuration (IOCON) 7.5.4 Type D IOCON registers (PIO1) This IOCON table applies to port pins P1[9 to 17]. Other pins include ADC or I C functions that alter the contents of the related IOCON registers.
Page 98 UM10850 NXP Semiconductors Chapter 7: LPC5410x I/O pin configuration (IOCON) Table 122. Type D I/O Control registers: FUNC values and pin functions Value of FUNC field in IOCON register Register 000 PIO1_9 PIO1_9 SPI0_MOSI CT32B0_CAP2 PIO1_10 PIO1_10 U1_TXD SCT0_OUT4 PIO1_11...
Page 99 UM10850 Chapter 8: LPC5410x Input multiplexing (INPUT MUX) Rev. 2.4 — 13 September 2016 User manual 8.1 How to read this chapter Input multiplexing is available for all parts. Depending on the package, not all inputs from external pins may be available.
Page 100 UM10850 NXP Semiconductors Chapter 8: LPC5410x Input multiplexing (INPUT MUX) 8.5.1 Pin interrupt input multiplexing The input mux for the pin interrupts and pattern match engine multiplexes all existing pins from ports 0 and 1. Fig 9. Pin interrupt multiplexing 8.5.2 DMA trigger input multiplexing...
Page 101 UM10850 NXP Semiconductors Chapter 8: LPC5410x Input multiplexing (INPUT MUX) 8.6 Register description All input mux registers reside on word address boundaries. Details of the registers appear in the description of each function. All address offsets not shown in Table 124 are reserved and should not be written to.
Page 102 UM10850 NXP Semiconductors Chapter 8: LPC5410x Input multiplexing (INPUT MUX) Table 124. Register overview: Input multiplexing (base address 0x4005 0000) …continued Name Access Offset Description Reset Reference value DMA_OTRIG_INMUX3 0x14C DMA output trigger selection to become DMA trigger 19 0x1F...
Page 103 UM10850 NXP Semiconductors Chapter 8: LPC5410x Input multiplexing (INPUT MUX) 8.6.2 DMA trigger input mux registers 0 to 21 With the DMA trigger input mux registers, one trigger input can be selected for each of the DMA channels from the potential internal sources. By default, none of the triggers are selected.
Page 104 UM10850 NXP Semiconductors Chapter 8: LPC5410x Input multiplexing (INPUT MUX) Table 130. DMA output trigger feedback mux registers (DMA_OTRIG_INMUX[0:3], address offset [0x140:0x14C]) bit description Symbol Description Reset value DMA trigger output number (decimal value) for DMA channel n 0x1F (n = 0 to 19).
Page 105 UM10850 NXP Semiconductors Chapter 8: LPC5410x Input multiplexing (INPUT MUX) 8.6.4 Frequency measure function reference clock select register This register selects a clock for the reference clock of the frequency measure function. By default, no clock is selected. See Section 4.6.5 “Frequency measure function”,...
Page 106 UM10850 Chapter 9: LPC5410x General Purpose I/O (GPIO) Rev. 2.4 — 13 September 2016 User manual 9.1 How to read this chapter GPIO registers support up to 32 pins on each port. Depending on the device and package type, a subset of those pins may be available, and the unused bits in GPIO registers are...
Page 107 UM10850 NXP Semiconductors Chapter 9: LPC5410x General Purpose I/O (GPIO) 9.5 Register description Note: In all GPIO registers, bits that are not shown are reserved. GPIO port addresses can be read and written as bytes, halfwords, or words. Remark: A reset value noted as “ext” in this table and subsequent tables indicates that the data read after reset depends on the state of the pin, which in turn may depend on an external source.
Page 108 UM10850 NXP Semiconductors Chapter 9: LPC5410x General Purpose I/O (GPIO) 9.5.1 GPIO port byte pin registers Each GPIO pin has a byte register in this address range. Software typically reads and writes bytes to access individual pins, but can read or write halfwords to sense or set the state of two pins, and read or write words to sense or set the state of four pins.
Page 109 UM10850 NXP Semiconductors Chapter 9: LPC5410x General Purpose I/O (GPIO) Table 139. Address map DIR[0:1] registers Peripheral Base address Offset Increment Dimension GPIO 0x1C00 0000 [0x2000:0x2004] Table 140. GPIO direction port register (DIR[0:1], address offset [0x2000:0x2004]) bit description Symbol Description...
Page 110 UM10850 NXP Semiconductors Chapter 9: LPC5410x General Purpose I/O (GPIO) 9.5.6 GPIO masked port pin registers These registers are similar to the PORT registers, except that the value read is masked by ANDing with the inverted contents of the corresponding MASK register, and writing to one...
Page 111 UM10850 NXP Semiconductors Chapter 9: LPC5410x General Purpose I/O (GPIO) Table 150. GPIO clear port register (CLR[0:1], address offset [0x2280:0x2284]) bit description Symbol Description Reset value Access 31:0 CLRP Clear output bits. Supported pins depends on the specific device and package.
Page 112 UM10850 NXP Semiconductors Chapter 9: LPC5410x General Purpose I/O (GPIO) 9.5.12 GPIO port direction toggle registers Direction bits can be set by writing ones to these write-only registers. Table 155. GPIO port direction toggle register (DIRNOT[0:1], offset 0x2480:0x2484) bit description...
Page 113 UM10850 NXP Semiconductors Chapter 9: LPC5410x General Purpose I/O (GPIO) 9.6 Functional description 9.6.1 Reading pin state Software can read the state of all GPIO pins except those selected for analog input or output in the “I/O Configuration” logic. A pin does not have to be selected for GPIO in “I/O Configuration”...
Page 114 UM10850 NXP Semiconductors Chapter 9: LPC5410x General Purpose I/O (GPIO) 9.6.3 Masked I/O A port’s MASK register defines which of its pins should be accessible in its MPORT register. Zeroes in MASK enable the corresponding pins to be read from and written to MPORT.
Page 115 Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) Rev. 2.4 — 13 September 2016 User manual 10.1 How to read this chapter The pin interrupt generator and the pattern match engine are available on all LPC5410x parts. 10.2 Features •...
Page 116 Follow these steps to configure pins as pin interrupts: 1. Determine the pins that serve as pin interrupts on the LPC5410x package. See the data sheet for determining the GPIO port pin number associated with the package pin. 2. For each pin interrupt, program the GPIO port pin number from ports 0 and 1 into one of the eight PINTSEL registers in the Input mux block.
Page 117 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) 10.4 Pin description The inputs to the pin interrupt and pattern match engine are determined by the pin interrupt select registers in the Input mux. See Section 8.6.1 “Pin interrupt select registers”.
Page 118 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) • Event (non-sticky): Every time an edge (rising or falling) is detected, the detect logic output for this pin goes HIGH. This bit is cleared after one clock cycle, and the detect logic can detect another edge, •...
Page 119 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) The pattern match logic continuously monitors the eight inputs and generates interrupts when any one or more minterms (product terms) of the specified boolean expression is matched. A separate interrupt request is generated for each individual minterm.
Page 120 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) 10.5.2.1 Example Assume the expression: (IN0)~(IN1)(IN3)^ + (IN1)(IN2) + (IN0)~(IN3)~(IN4) is specified through the registers PMSRC (Table 168) and PMCFG (Table 169). Each term in the boolean expression, (IN0), ~(IN1), (IN3)^, etc., represents one bit slice of the pattern match engine.
Page 121 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) 10.6 Register description Table 156. Register overview: Pin interrupts/pattern match engine (base address: 0x4001 8000) Name Access Address Description Reset Reference offset value ISEL 0x000 Pin Interrupt Mode register...
Page 122 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) 10.6.1 Pin interrupt mode register For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 126), one bit in the ISEL register determines whether the interrupt is edge or level sensitive.
Page 123 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) 10.6.4 Pin interrupt level or rising edge interrupt clear register For each of the 8 pin interrupts selected in the PINTSELn registers (see Table 126), one bit in the CIENR register clears the corresponding bit in the IENR register depending on the pin interrupt mode configured in the ISEL register: •...
Page 124 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) Table 162. Pin interrupt active level or falling edge interrupt set register (SIENF, address 0x4001 8014) bit description Symbol Description Reset value Access SETENAF Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n sets bit n in the IENF register.
Page 125 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) 10.6.9 Pin interrupt falling edge register This register contains ones for pin interrupts selected in the PINTSELn registers (see Table 126) on which a falling edge has been detected. Writing ones to this register clears falling edge detection.
Page 126 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) Remark: note that the pattern match feature requires clocks in order to operate, and can thus not generate an interrupt or wake up the device during reduced power modes below Sleep mode.
Page 127 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) Table 168. Pattern match bit-slice source register (PMSRC, address 0x4001 802C) bit description Symbol Value Description Reset value 13:11 SRC1 Selects the input source for bit slice 1 Input 0.
Page 128 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) Table 168. Pattern match bit-slice source register (PMSRC, address 0x4001 802C) bit description Symbol Value Description Reset value 25:23 SRC5 Selects the input source for bit slice 5 Input 0.
Page 129 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) • Non-sticky: Every time an edge (rising or falling) is detected, the detect logic output for this pin goes HIGH. This bit is cleared after one clock cycle, and the edge detect...
Page 130 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) Table 169. Pattern match bit slice configuration register (PMCFG, address 0x4001 8030) bit description …continued Symbol Value Description Reset value Reserved. Bit slice 7 is automatically considered a product end point.
Page 131 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) Table 169. Pattern match bit slice configuration register (PMCFG, address 0x4001 8030) bit description …continued Symbol Value Description Reset value 16:14 CFG2 Specifies the match contribution condition for bit slice 2.
Page 132 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) Table 169. Pattern match bit slice configuration register (PMCFG, address 0x4001 8030) bit description …continued Symbol Value Description Reset value 22:20 CFG4 Specifies the match contribution condition for bit slice 4.
Page 133 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) Table 169. Pattern match bit slice configuration register (PMCFG, address 0x4001 8030) bit description …continued Symbol Value Description Reset value 28:26 CFG6 Specifies the match contribution condition for bit slice 6.
Page 134 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) 10.7 Functional description 10.7.1 Pin interrupts In this interrupt facility, up to 8 pins are identified as interrupt sources by the Pin Interrupt Select registers (PINTSEL0-7). All registers in the pin interrupt block contain 8 bits, corresponding to the pins called out by the PINTSEL0-7 registers.
Page 135 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) – SRC7: 111 - select input 7 for bit slice 7 • PMCFG register (Table 169): – PROD_ENDPTS0 = 1 – PROD_ENDPTS02 = 1 – PROD_ENDPTS5 = 1 –...
Page 136 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) 10.7.3 Pattern match engine edge detect examples Figure shows pattern match functionality only and accurate timing is not implied. Inputs (INn) are shown synchronized to the system clock for simplicity.
Page 137 UM10850 NXP Semiconductors Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) Figure shows pattern match functionality only and accurate timing is not implied. Inputs (INn) are shown synchronized to the system clock for simplicity. Fig 16. Pattern match engine examples: Windowed non-sticky edge detect evaluates as false UM10850 All information provided in this document is subject to legal disclaimers.
Page 138 UM10850 Chapter 11: LPC5410x Group GPIO input interrupt (GINT0/1) Rev. 2.4 — 13 September 2016 User manual 11.1 Features • The inputs from any number of digital pins can be enabled to contribute to a combined group interrupt. • The polarity of each input enabled for the group interrupt can be configured HIGH or LOW.
Page 139 UM10850 NXP Semiconductors Chapter 11: LPC5410x Group GPIO input interrupt (GINT0/1) 11.4 Register description Note: In all registers, bits that are not shown are reserved. Table 171. Register overview: GROUP0 interrupt (base address 0x4001 0000 (GINT0) and 0x4001 4000 (GINT1))
Page 140 UM10850 NXP Semiconductors Chapter 11: LPC5410x Group GPIO input interrupt (GINT0/1) 11.4.1 Grouped interrupt control register Table 172. GPIO grouped interrupt control register (CTRL, addresses 0x4001 0000 (GINT0) and 0x4001 4000 (GINT1)) bit description Symbol Value Description Reset value Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect.
Page 141 UM10850 NXP Semiconductors Chapter 11: LPC5410x Group GPIO input interrupt (GINT0/1) Table 174. GPIO grouped interrupt port enable registers (PORT_ENA[0:1], addresses 0x4001 0040 (PORT_ENA0) to 0x4001 0044 (PORT_ENA1) (GINT0) and 0x4001 4040 (PORT_ENA0) to 0x4001 4044 (PORT_ENA1) (GINT1)) bit description...
Page 142 UM10850 Chapter 12: LPC5410x DMA controller Rev. 2.4 — 13 September 2016 User manual 12.1 How to read this chapter The DMA controller is available on all parts. 12.2 Features • 22 channels, 21 of which are connected to peripheral DMA requests. These come from the USART, SPI, and I C peripherals.
Page 143 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller 12.3.1 Hardware triggers Each DMA channel can use one trigger that is independent of the request input for this channel. The trigger input is selected in the DMA_ITRIG_INMUX registers. There are 20 possible internal trigger sources for each channel with each trigger signal issued by the output of a peripheral.
Page 144 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller 12.3.3 DMA requests DMA requests are directly connected to the peripherals. Each channel supports one DMA request line and one trigger input which is multiplexed to many possible input sources, as shown in Table 176.
Page 145 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller 12.4 Pin description The DMA controller has no configurable pins. 12.5 General description Fig 17. DMA block diagram 12.5.1 DMA requests and triggers An operation on a DMA channel can be initiated by either a DMA request or a trigger event.
Page 146 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller can range from a single transfer to many transfers. A transfer that is started by a trigger can still be paced using the channel’s DMA request. This allows sending a string to a serial peripheral, for instance, without overrunning the peripheral’s transmit buffer.
Page 147 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller 12.5.3 Single buffer This generally applies to memory to memory moves, and peripheral DMA that occurs only occasionally and is set up for each transfer. For this kind of operation, only the initial...
Page 148 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller Table 180: Example descriptors for ping-pong operation: peripheral to buffer Channel Descriptor Descriptor B Descriptor A + 0x0 (not used) + 0x0 Buffer B transfer configuration + 0x0 Buffer A transfer configuration...
Page 149 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller – If channel x is configured to auto reload the descriptor on exhausting of the descriptor (bit RELOAD in the transfer configuration of the descriptor is set), then enable ‘clear trigger on descriptor exhausted’ by setting bit CLRTRIG in the channel’s transfer configuration in the descriptor.
Page 150 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller 12.6 Register description The DMA registers are grouped into DMA control, interrupt and status registers and DMA channel registers. DMA transfers are controlled by a set of three registers per channel, the CFG[0:20], CTRLSTAT[0:20], and XFERCFG[0:20] registers.
Page 151 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller Table 181. Register overview: DMA controller (base address 0x1C00 4000) Name Access Address Description Reset Reference offset value Channel 4 registers CFG4 0x440 Configuration register for DMA channel 4. Table 199 CTLSTAT4 0x444 Control and status register for DMA channel 4.
Page 152 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller Table 181. Register overview: DMA controller (base address 0x1C00 4000) Name Access Address Description Reset Reference offset value Channel 14 registers CFG14 0x4E0 Configuration register for DMA channel 14. Table 199 CTLSTAT14 0x4E4 Control and status register for DMA channel 14.
Page 153 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller 12.6.1 Control register The CTRL register contains global the control bit for a enabling the DMA controller. Table 182. Control register (CTRL, address 0x1C00 4000) bit description Symbol Value Description Reset value ENABLE DMA controller master enable.
Page 154 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller Table 185. Channel descriptor map Descriptor Table offset Channel descriptor for DMA channel 0 0x000 Channel descriptor for DMA channel 1 0x010 Channel descriptor for DMA channel 2 0x020 Channel descriptor for DMA channel 3...
Page 155 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller Table 187. Enable Clear register 0 (ENABLECLR0, address 0x1C00 4028) bit description Symbol Description Reset value 21:0 Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.
Page 156 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller 12.6.8 Error Interrupt register The ERRINT0 register contains flags for each DMA channel’s Error Interrupt. Any pending interrupt flag in the register will be reflected on the DMA interrupt output. Reading the registers provides the current state of all DMA channel error interrupts.
Page 157 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller Table 193. Interrupt A register 0 (INTA0, address 0x1C00 4058) bit description Symbol Description Reset value 21:0 Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. 0 = the DMA channel interrupt A is not active.
Page 158 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller Table 196. Set Trigger 0 register (SETTRIG0, address 0x1C00 4070) bit description Symbol Description Reset value 21:0 TRIG Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n.
Page 159 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller 12.6.16 Channel configuration registers The CFGn register contains various configuration options for DMA channel n. Table 200 for a summary of trigger options. Table 198. Address map CFG[0:21] registers Peripheral Base address...
Page 160 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller Table 199. Channel configuration registers bit description Symbol Value Description Reset value 11:8 BURSTPOWER Burst Power is used in two ways. It always selects the address wrap size when SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register).
Page 161 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller Table 200. Trigger setting summary TrigBurst TrigType TrigPol Description Hardware DMA trigger is high level sensitive. The BURSTPOWER field controls address wrapping if enabled via SrcBurstWrap and/or DstBurstWrap. Hardware DMA trigger is falling edge sensitive. The BURSTPOWER field controls address wrapping if enabled via SrcBurstWrap and/or DstBurstWrap, and also determines how much data is transferred for each trigger.
Page 162 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller 12.6.18 Channel transfer configuration registers The XFERCFGn register contains transfer related configuration information for DMA channel n. Using the Reload bit, this register can optionally be automatically reloaded when the current settings are exhausted (the full transfer count has been completed), allowing linked transfers with more than one descriptor to be performed.
Page 163 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller Table 204. Channel transfer configuration registers bit description Symbol Value Description Reset Value SETINTB Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage.
Page 164 UM10850 NXP Semiconductors Chapter 12: LPC5410x DMA controller 12.7 Functional description 12.7.1 Trigger operation A trigger of some kind is always needed to start a transfer on a DMA channel. This can be a hardware or software trigger, and can be used in several ways.
Page 165 UM10850 Chapter 13: LPC5410x SCTimer/PWM (SCT0) Rev. 2.4 — 13 September 2016 User manual 13.1 How to read this chapter The SCTimer/PWM is available on all parts. Remark: For a detailed description of SCTimer/PWM applications and code examples, Ref. 3 “AN11538”.
Page 166 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) • State control features: – A state is defined by events that can happen in the state while the counter is running. – A state changes into another state as a result of an event.
Page 167 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) 13.4 Pin description Chapter 7 to assign the SCT functions to external pins. SCT input signals are predefined. The signals from external pins and internal signals are connected directly to the SCT inputs and not routed through IOCON.
Page 168 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) Table 208: Suggested SCT output pin settings IOCON Type D pin Type A pin Type I pin bit(s) OD: Set to 0 unless open-drain output is desired. Same as type D. I2CFILTER: Set to 1 SLEW: Set to 0.
Page 169 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) driven as well and can therefore happen without software intervention. By defining these states, the SCTimer/PWM provides the means to run entire state machines in hardware with any desired level of complexity to accomplish complex waveform and timing tasks.
Page 170 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) Fig 21. SCTimer/PWM counter and select logic Remark: In this chapter, the term bus error indicates an SCT response that makes the processor take an exception. 13.6 Register description The register addresses of the State Configurable Timer are shown in Table 209.
Page 171 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) Table 209. Register overview: State Configurable Timer SCT/PWM (base address 0x5000 4000) Name Access Offset Description Reset value Reference CONFIG 0x000 SCT configuration register 0x0000 7E00 Table 210 CTRL 0x004 SCT control register...
Page 172 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) Table 209. Register overview: State Configurable Timer SCT/PWM (base address 0x5000 4000) …continued Name Access Offset Description Reset value Reference MATCH0_H to 0x102 to SCT match value register of match channels 0 to...
Page 173 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) Table 209. Register overview: State Configurable Timer SCT/PWM (base address 0x5000 4000) …continued Name Access Offset Description Reset value Reference EV10_STATE 0x350 SCT event state register 10 0x0000 0000 Table 233 EV10_CTRL...
Page 174 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) select one event m MATCH MATCHSEL MATCH[i:0] COMBMODE change state select one STATELD/ IOSEL EVm_CTRL STATEV in bidirectional mode, inputs select counter direction DIRECTION SCT_IN[q:0] outputs select in which states the event is allowed...
Page 175 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) 13.6.1.1 Counter configuration and control registers The SCT contains two registers for configuring the SCT and monitor and control its operation by software. • The configuration register (CONFIG) configures the SCT in single, 32-bit counter mode or in dual, 16-bit counter mode, configures the clocking and clock synchronization, and configures automatic limits and the use of reload registers.
Page 176 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) 13.6.1.5 Event select registers for setting or clearing the outputs This group contains the registers that select the events which affect the level of each SCT output. Also included are registers to manage conflicts that occur when events try to set or clear the same output.
Page 177 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) 13.6.2 SCT configuration register This register configures the overall operation of the SCT. Write to this register before any other registers. Only word-writes are permitted to this register. Attempting to write a half-word value results in a bus error.
Page 178 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) Table 210. SCT configuration register (CONFIG, address 0x5000 4000) bit description …continued Symbol Value Description Reset value 12:9 INSYNC Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 12 = input 3); all other bits are reserved.
Page 179 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) Table 211. SCT control register (CTRL, address 0x5000 4004) bit description Symbol Value Description Reset value DOWN_L This bit is 1 when the L or unified counter is counting down. Hardware sets this bit when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware...
Page 180 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) Table 211. SCT control register (CTRL, address 0x5000 4004) bit description Symbol Value Description Reset value BIDIR_H Direction select The H counter counts up to its limit condition, then is cleared to zero.
Page 181 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) Each bit of the register is associated with a different event (bit 0 with event 0, etc.). Setting a bit will cause its associated event to serve as a HALT event. To define the actual events that cause the counter to halt (a match, an I/O pin toggle, etc.), see the EVn_CTRL...
Page 182 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) Each bit of the register is associated with a different event (bit 0 with event 0, etc.). Setting a bit will cause its associated event to serve as a START event. When any START event occurs, hardware will clear the STOP bit in the Control Register CTRL.
Page 183 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) The state variable is the main feature that distinguishes the SCTimer/PWM from other counter/timer/ PWM blocks. Events can be made to occur only in certain states. Events, in turn, can perform the following actions: •...
Page 184 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) Table 218. SCT input register (INPUT, address 0x5000 4048) bit description Symbol Description Reset value AIN0 Input 0 state. Input 0 state on the last SCT clock edge. AIN1 Input 1 state. Input 1 state on the last SCT clock edge.
Page 185 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) all counters (L-counter, H-counter, or unified counter) are halted (HALT bits are set to 1 in the CTRL register). Software can read this register at any time to sense the state of the outputs.
Page 186 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) 13.6.14 SCT conflict resolution register The output conflict resolution register specifies what action should be taken if multiple events (or even the same event) dictate that a given output should be both set and cleared at the same time.
Page 187 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) Event-triggered DMA requests are particularly useful for launching DMA activity to or from other peripherals under the control of the SCT. Table 223. SCT DMA 0 request register (DMAREQ0, address 0x5000 405C) bit description...
Page 188 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) 13.6.18 SCT conflict interrupt enable register This register enables the no-change conflict events specified in the SCT conflict resolution register to generate an interrupt request. Table 227. SCT conflict interrupt enable register (CONEN, address 0x5000 40F8) bit description...
Page 189 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) Table 229. SCT match registers 0 to 12 (MATCH[0:12], address 0x5000 4100 (MATCH0) to 0x5000 4130 (MATCH12)) bit description (REGMODEn bit = 0) Symbol Description Reset value 15:0 MATCHn_L When UNIFY = 0, read or write the 16-bit value to be compared to the L counter.
Page 190 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) If UNIFY = 0 in the CONFIG register, this register can be written to as two registers CAPCTRLn_L and CAPCTRLn_H. Both the L and H registers can be read or written individually or in a single 32-bit read or write operation.
Page 191 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) An event can be programmed to occur based on a selected input or output edge or level and/or based on its counter value matching a selected match register. In bi-directional mode, events can also be enabled based on the direction of count.
Page 192 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) Table 234. SCT event control register 0 to 12 (EV[0:12]_CTRL, address 0x5000 4304 (EV0_CTRL) to 0x5000 4364 (EV12_CTRL)) bit description Symbol Value Description Reset value MATCHMEM If this bit is one and the COMBMODE field specifies a match component to the...
Page 193 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) Remark: If the SCTimer/PWM is operating as two 16-bit counters, events can only modify the state of the outputs when neither counter is halted. This is true regardless of what triggered the event.
Page 194 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) 13.7 Functional description 13.7.1 Match logic Fig 23. Match logic 13.7.2 Capture logic Fig 24. Capture logic 13.7.3 Event selection State variables allow control of the SCT across more than one cycle of the counter.
Page 195 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) Fig 25. Event selection 13.7.4 Output generation Figure 26 shows one output slice of the SCT. Fig 26. Output slice i 13.7.5 State logic The SCT can be configured as a timer/counter with multiple programmable states. The states are user-defined through the events that can be captured in each particular state.
Page 196 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) Software can capture the counter value (and potentially create an interrupt and write to all outputs) when the event moving the SCT into a locked state occurs.Later, while the SCT is in the locked state, software can read the counter again to record the time passed since...
Page 197 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) • The prescaler is enabled when the clock mode is not 01, or when the input edge selected by the CLKSEL field is detected. • The counter is enabled when the prescaler is enabled, and (PRELIM=0 or the prescaler is equal to the value in PRELIM).
Page 198 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) 13.7.10 Configure the SCT To set up the SCT for multiple events and states, perform the following configuration steps: 13.7.10.1 Configure the counter 1. Configure the L and H counters in the CONFIG register by selecting two independent 16-bit counters (L counter and H counter) or one combined 32-bit counter in the UNIFY field.
Page 199 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) – Set the corresponding event bit in the LIMIT register for the event to set an upper limit for the counter. When a limit event occurs in unidirectional mode, the counter is cleared to zero and begins counting up on the next clock edge.
Page 200 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) 3. To start the SCT, write to the CTRL register: – Clear the counters. – Clear or set the STOP_L and/or STOP_H bits. Remark: The counter starts counting once the STOP bit is cleared as well. If the STOP bit is set, the SCT waits instead for an event to occur that is configured to start the counter.
Page 201 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) same output but triggered by different match values. If input 0 is found HIGH by the next time the timer is reset, the associated event (EV5) causes the state to change back to state 0where the events EV0 and EV1 are enabled.
Page 202 UM10850 NXP Semiconductors Chapter 13: LPC5410x SCTimer/PWM (SCT0) Table 238. SCT configuration example Configuration Registers Setting Define match values MATCH Set a match value MATCH0/1/2/4/5_L in each register. The match 0 register 0/1/2/3/4 serves as an automatic limit event that resets the counter. without using an event.
Page 203 Rev. 2.4 — 13 September 2016 User manual 14.1 How to read this chapter These five standard timers are available on all LPC5410x parts. 14.2 Basic configuration • Set the appropriate bits to enable clocks to timers that will be used: CT32B0 and CT32B1 in the ASYNCAPBCLKCTRL register, CT32B2, CT32B3, and CT32B4 in the AHBCLKCTRL1 register.
Page 204 UM10850 NXP Semiconductors Chapter 14: LPC5410x Standard counter/timers (CT32B0/1/2/3/4) • PWM: for each timer with pin connections, up to 3 match outputs can be used as single edge controlled PWM outputs. 14.4 Applications • Interval Timer for counting internal events.
Page 205 UM10850 NXP Semiconductors Chapter 14: LPC5410x Standard counter/timers (CT32B0/1/2/3/4) Fig 29. 32-bit counter/timer block diagram UM10850 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved. User manual Rev. 2.4 — 13 September 2016...
Page 206 UM10850 NXP Semiconductors Chapter 14: LPC5410x Standard counter/timers (CT32B0/1/2/3/4) 14.6 Pin description Table 239 gives a brief summary of each of the Timer/Counter related pins. Recommended IOCON settings are shown in Table 240. Table 239. Timer/Counter pin description Type Description...
Page 207 UM10850 NXP Semiconductors Chapter 14: LPC5410x Standard counter/timers (CT32B0/1/2/3/4) 14.7 Register description Each Timer/Counter contains the registers shown in Table 241 ("Reset Value" refers to the data stored in used bits only; it does not include reserved bits content). More detailed descriptions follow.
Page 208 UM10850 NXP Semiconductors Chapter 14: LPC5410x Standard counter/timers (CT32B0/1/2/3/4) 14.7.1 Interrupt Register The Interrupt Register consists of 4 bits for the match interrupts and 4 bits for the capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be high.
Page 209 UM10850 NXP Semiconductors Chapter 14: LPC5410x Standard counter/timers (CT32B0/1/2/3/4) Table 245. Timer Control Register (TCR, address offset 0x004) bit description Symbol Value Description Reset value CRST Counter reset. Disabled. Do nothing. Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK.
Page 210 UM10850 NXP Semiconductors Chapter 14: LPC5410x Standard counter/timers (CT32B0/1/2/3/4) 14.7.4 Prescale register The 32-bit Prescale register specifies the maximum value for the Prescale Counter. Table 248. Address map PR register Peripheral Base address Offset Increment Dimension CT32B0 0x400B 4000 0x00C...
Page 211 UM10850 NXP Semiconductors Chapter 14: LPC5410x Standard counter/timers (CT32B0/1/2/3/4) Table 252. Address map MCR register Peripheral Base address Offset Increment Dimension CT32B2 0x4000 4000 0x014 CT32B3 0x4000 8000 0x014 CT32B4 0x4000 C000 0x014 Table 253. Match Control Register (MCR, address offset 0x014) bit description...
Page 212 UM10850 NXP Semiconductors Chapter 14: LPC5410x Standard counter/timers (CT32B0/1/2/3/4) Table 255. Timer match registers (MR[0:3], address offset [0x018:0x024]) bit description Symbol Description Reset value 31:0 MATCH Timer counter match value. 14.7.8 Capture Control Register The Capture Control Register is used to control whether one of the four Capture Registers is loaded with the value in the Timer Counter when the capture event occurs, and whether an interrupt is generated by the capture event.
Page 213 UM10850 NXP Semiconductors Chapter 14: LPC5410x Standard counter/timers (CT32B0/1/2/3/4) 14.7.9 Capture Registers Each Capture register is associated with one capture channel and may be loaded with the counter/timer value when a specified event occurs on the signal defined for that capture channel.
Page 214 UM10850 NXP Semiconductors Chapter 14: LPC5410x Standard counter/timers (CT32B0/1/2/3/4) Table 261. Timer external match registers (EMR, address offset 0x03C) bit description Symbol Value Description Reset value External Match 0. This bit reflects the state of output MAT0, whether or not this output is connected to a pin.
Page 215 UM10850 NXP Semiconductors Chapter 14: LPC5410x Standard counter/timers (CT32B0/1/2/3/4) 14.7.11 Count Control Register The Count Control Register (CTCR) is used to select between Timer and Counter mode, and in Counter mode to select the pin and edge(s) for counting. When Counter Mode is chosen as a mode of operation, the CAP input (selected by the CTCR bits 3:2) is sampled on every rising edge of the PCLK clock.
Page 216 UM10850 NXP Semiconductors Chapter 14: LPC5410x Standard counter/timers (CT32B0/1/2/3/4) Table 263. Count Control Register (CTCR, address offset 0x070) bit description Symbol Value Description Reset Value CINSEL Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking.
Page 217 UM10850 NXP Semiconductors Chapter 14: LPC5410x Standard counter/timers (CT32B0/1/2/3/4) Table 264. Address map PWMC register Peripheral Base address Offset Increment Dimension CT32B2 0x4000 4000 0x074 CT32B3 0x4000 8000 0x074 CT32B4 0x4000 C000 0x074 Table 265: PWM Control Register (PWMC, address offset 0x074)) bit description...
Page 218 UM10850 NXP Semiconductors Chapter 14: LPC5410x Standard counter/timers (CT32B0/1/2/3/4) Fig 31. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled 14.8.1 Rules for single edge controlled PWM outputs 1. All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle (timer is set to zero) unless their match value is equal to zero.
Page 219 UM10850 NXP Semiconductors Chapter 14: LPC5410x Standard counter/timers (CT32B0/1/2/3/4) 14.8.2 DMA operation DMA requests are generated by a match of the Timer Counter (TC) register value to either Match Register 0 (MR0) or Match Register 1 (MR1). This is not connected to the operation of the Match outputs controlled by the EMR register.
Page 220 Chapter 15: LPC5410x Windowed Watchdog Timer (WWDT) Rev. 2.4 — 13 September 2016 User manual 15.1 How to read this chapter The watchdog timer is identical on all LPC5410x parts. 15.2 Features • Internally resets chip if not reloaded during the programmable time-out period.
Page 221 UM10850 NXP Semiconductors Chapter 15: LPC5410x Windowed Watchdog Timer (WWDT) 15.3 Basic configuration The WWDT is configured through the following registers: • Power to the register interface (WWDT PCLK clock): set the WWDT bit in the AHBCLKCTRL0 register, Table •...
Page 222 UM10850 NXP Semiconductors Chapter 15: LPC5410x Windowed Watchdog Timer (WWDT) • Set a value for the watchdog warning interrupt in the WARNINT register if a warning interrupt is desired. • Enable the Watchdog by writing 0xAA followed by 0x55 to the FEED register.
Page 223 UM10850 NXP Semiconductors Chapter 15: LPC5410x Windowed Watchdog Timer (WWDT) 15.5.2 Clocking and power control The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB accesses to the watchdog registers and is derived from the system clock (see...
Page 224 UM10850 NXP Semiconductors Chapter 15: LPC5410x Windowed Watchdog Timer (WWDT) 15.6 Register description The Watchdog Timer contains the registers shown in Table 266. The reset value reflects the data stored in used bits only. It does not include the content of reserved bits.
Page 225 UM10850 NXP Semiconductors Chapter 15: LPC5410x Windowed Watchdog Timer (WWDT) Table 267. Watchdog mode register (MOD, 0x4003 8000) bit description Symbol Value Description Reset value WDPROTECT Watchdog update mode. This bit can be set once by software and is only cleared by a reset.
Page 226 UM10850 NXP Semiconductors Chapter 15: LPC5410x Windowed Watchdog Timer (WWDT) 15.6.2 Watchdog Timer Constant register The TC register determines the time-out value. Every time a feed sequence occurs the value in the TC is loaded into the Watchdog timer. The TC resets to 0x00 00FF. Writing a value below 0xFF will cause 0x00 00FF to be loaded into the TC.
Page 227 UM10850 NXP Semiconductors Chapter 15: LPC5410x Windowed Watchdog Timer (WWDT) 15.6.5 Watchdog Timer Warning Interrupt register The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog interrupt. When the watchdog timer counter matches the value defined by WARNINT, an interrupt will be generated after the subsequent WDCLK.
Page 228 UM10850 NXP Semiconductors Chapter 15: LPC5410x Windowed Watchdog Timer (WWDT) 15.7 Functional description The following figures illustrate several aspects of Watchdog Timer operation. Fig 35. Early watchdog feed with windowed mode enabled Fig 36. Correct watchdog feed with windowed mode enabled Fig 37.
Page 229 Chapter 16: LPC5410x Real-Time Clock (RTC) Rev. 2.4 — 13 September 2016 User manual 16.1 How to read this chapter The RTC is identical on all LPC5410x parts. 16.2 Features • The RTC and its independent oscillator operate directly from the device power pins, not using the on-chip regulator.
Page 230 UM10850 NXP Semiconductors Chapter 16: LPC5410x Real-Time Clock (RTC) Fig 38. RTC clocking 16.3.1 RTC timers The RTC contains two timers: 1. The main RTC timer. This 32-bit timer uses a 1 Hz clock and is intended to run continuously as a real-time clock. When the timer value reaches a match value, an interrupt is raised.
Page 231 UM10850 NXP Semiconductors Chapter 16: LPC5410x Real-Time Clock (RTC) 16.4 General description 16.4.1 Real-time clock The real-time clock is a 32-bit up-counter which can be cleared or initialized by software. Once enabled, it counts continuously at a 1 Hz clock rate as long as the device is powered up and the RTC remains enabled.
Page 232 UM10850 NXP Semiconductors Chapter 16: LPC5410x Real-Time Clock (RTC) 16.6 Register description Reset Values pertain to initial power-up of the device or when an RTC software reset is applied (except where noted). This block is not initialized by any other system reset.
Page 233 UM10850 NXP Semiconductors Chapter 16: LPC5410x Real-Time Clock (RTC) Table 276. RTC control register (CTRL, address 0x4003 C000) bit description Symbol Value Description Reset value ALARMDPD_EN RTC 1 Hz timer alarm enable for Deep power-down. Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode.
Page 234 UM10850 NXP Semiconductors Chapter 16: LPC5410x Real-Time Clock (RTC) 16.6.4 RTC high-resolution/wake-up register Table 279. RTC high-resolution/wake-up register (WAKE, address 0x4003 C00C) bit description Symbol Description Reset value 15:0 A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads a start count value into the wake-up timer and initializes a count-down sequence.
Page 235 UM10850 Chapter 17: LPC5410x Multi-Rate Timer (MRT) Rev. 2.4 — 13 September 2016 User manual 17.1 How to read this chapter The MRT is available on all LPC5410x parts. 17.2 Features • 24-bit interrupt timer clocked from CPU clock •...
Page 236 UM10850 NXP Semiconductors Chapter 17: LPC5410x Multi-Rate Timer (MRT) Fig 39. MRT block diagram 17.5.1 Repeat interrupt mode The repeat interrupt mode generates repeated interrupts after a selected time interval. This mode can be used for software-based PWM or PPM applications.
Page 237 UM10850 NXP Semiconductors Chapter 17: LPC5410x Multi-Rate Timer (MRT) • Update the INTVALn register with a new time interval value (>0) and set the LOAD bit to 1. The timer immediately reloads the new time interval, and starts counting down from the new value.
Page 238 UM10850 NXP Semiconductors Chapter 17: LPC5410x Multi-Rate Timer (MRT) 17.6 Register description The reset values shown in Table 280 are POR reset values. Table 280. Register overview: MRT (base address 0x4007 4000) Name Access Address Description Reset Reference offset value...
Page 239 UM10850 NXP Semiconductors Chapter 17: LPC5410x Multi-Rate Timer (MRT) 17.6.1 Time interval register (INTVAL) This register contains the MRT load value and controls how the timer is reloaded. The load value is IVALUE -1. Table 281. Time interval register (INTVAL[0:3], address 0x4007 4000 (INTVAL0) to 0x4007 4030 (INTVAL3)) bit...
Page 240 UM10850 NXP Semiconductors Chapter 17: LPC5410x Multi-Rate Timer (MRT) 17.6.3 Control register (CTRL) The control register configures the mode for each MRT and enables the interrupt. Table 283. Control register (CTRL[0:3], address 0x4007 4008 (CTRL0) to 0x4007 4038 (CTRL3)) bit description...
Page 241 UM10850 NXP Semiconductors Chapter 17: LPC5410x Multi-Rate Timer (MRT) 17.6.5 Module Configuration register (MODCFG) The MODCFG register provides the configuration (number of channels and timer width) for this MRT. See Section 17.6.6 “Idle channel register (IDLE_CH)” for details. Table 285. Module Configuration register (MODCFG, address 0x4007 40F0) bit description...
Page 242 UM10850 NXP Semiconductors Chapter 17: LPC5410x Multi-Rate Timer (MRT) 17.6.7 Global interrupt flag register (IRQ_FLAG) The global interrupt register combines the interrupt flags from the individual timer channels in one register. Setting and clearing each flag behaves in the same way as setting and clearing the INTFLAG bit in each of the STATUSn registers.
Page 243 UM10850 Chapter 18: LPC5410x Repetitive Interrupt Timer (RIT) Rev. 2.4 — 13 September 2016 User manual 18.1 How to read this chapter 18.2 Basic configuration The RI timer is configured through the following registers: • Power to the register interface: set the RIT bit in the AHBCLKCTRL1 register, Table 18.3 Features...
Page 244 UM10850 NXP Semiconductors Chapter 18: LPC5410x Repetitive Interrupt Timer (RIT) Fig 40. Repetitive Interrupt Timer (RI Timer) block diagram UM10850 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved. User manual Rev.
Page 245 UM10850 NXP Semiconductors Chapter 18: LPC5410x Repetitive Interrupt Timer (RIT) 18.5 Register description Table 288. Register overview: Repetitive Interrupt Timer (RIT) (base address 0x4007 0000) Name Access Offset Description Reset value Reference COMPVAL 0x000 Compare value LSB register. Holds the 32 LSBs of the...
Page 246 UM10850 NXP Semiconductors Chapter 18: LPC5410x Repetitive Interrupt Timer (RIT) Table 291. RI Control register (CTRL, address 0x4007 0008) bit description Symbol Value Description Reset value RITENCLR Timer enable clear The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of COMPVAL/COMPVAL_H and MASK/MASK_H registers.
Page 247 UM10850 NXP Semiconductors Chapter 18: LPC5410x Repetitive Interrupt Timer (RIT) 18.5.7 RI Counter MSB register Table 295. RI Counter MSB register (COUNTER_H, address 0x4007 001C) bit description Symbol Description Reset value 15:0 RICOUNTER 16 LSBs of the up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL).
Page 248 Rev. 2.4 — 13 September 2016 User manual 19.1 How to read this chapter The system tick timer (SysTick timer) is present on all LPC5410x devices in both the ARM Cortex-M4 and ARM Cortex-M0+ cores (when the Cortex-M0+ is present on LPC54102 devices).
Page 249 UM10850 NXP Semiconductors Chapter 19: LPC5410x CPU system tick timer (SYSTICK) Fig 41. System tick timer block diagram The SysTick timer is an integral part of both the Cortex-M4 and Cortex-M0+ (if present). The SysTick timer is intended to generate a fixed 10 millisecond interrupt for use by an operating system or other system management software.
Page 250 UM10850 NXP Semiconductors Chapter 19: LPC5410x CPU system tick timer (SYSTICK) 19.5 Register description The systick timer registers are located on the private peripheral bus of each CPU (see Figure Table 296. Register overview: SysTick timer (base address 0xE000 E000)
Page 251 UM10850 NXP Semiconductors Chapter 19: LPC5410x CPU system tick timer (SYSTICK) 19.5.3 System Timer Current value register The SYST_CVR register returns the current count from the System Tick counter when it is read by software. Table 299. System Timer Current value register (SYST_CVR - 0xE000 E018) bit description...
Page 252 UM10850 NXP Semiconductors Chapter 19: LPC5410x CPU system tick timer (SYSTICK) 19.6 Functional description The SysTick timer is a 24-bit timer that counts down to zero and generates an interrupt. The intent is to provide a fixed 10 millisecond time interval between interrupts. The...
Page 253 UM10850 Chapter 20: LPC5410x Micro-tick timer (UTICK) Rev. 2.4 — 13 September 2016 User manual 20.1 How to read this chapter The Micro-Tick Timer is available on all LPC5410x devices. 20.2 Features • Ultra simple timer. • Write once to start.
Page 254 UM10850 NXP Semiconductors Chapter 20: LPC5410x Micro-tick timer (UTICK) 20.5 Register description The Micro-Tick Timer contains the registers shown in Table 301. Note that the Micro-Tick Timer operates from a different (typically slower) clock than the CPU and bus systems.
Page 255 UM10850 Chapter 21: LPC5410x USARTs (USART0/1/2/3) Rev. 2.4 — 13 September 2016 User manual 21.1 How to read this chapter Read this chapter for a description of the USART peripheral and the software interface. 21.2 Features • 7, 8, or 9 data bits and 1 or 2 stop bits.
Page 256 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) 21.3 Basic configuration If using the USARTs with FIFO support, configure the FIFOs, see Chapter Configure USARTs for receiving and transmitting data: • In the ASYNCAPBCLKCTRL register, set bit 1 to 4...
Page 257 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) The USART can also be clocked by the 32 kHz RTC oscillator. Set the MODE32K bit to enable this 32 kHz mode. See also Section 21.7.1.4 “32 kHz mode”. Fig 43. USART clocking For details on the clock configuration see: Section 21.7.1 “Clocking and baud rates”...
Page 258 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) 21.3.2.2 Wake-up from Deep-sleep or Power-down mode • Configure the USART in synchronous slave mode. See Table 307. The SCLK function must be connected to a pin and also connect the pin to the master. Alternatively, the 32 kHz mode can be enabled and the USART operated in asynchronous mode with the 32 kHz RTC oscillator.
Page 259 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) 21.4 Pin description The USART receive, transmit, and control signals are movable functions and are assigned to external pins through via IOCON. See the IOCON description (Chapter 7) to assign the USART functions to pins on the device package.
Page 260 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) Table 305: Suggested USART pin settings IOCON Type D pin Type A pin Type I pin bit(s) MODE: Set 00 (to pull-down/pull-up resistor not Same as type D. Not used, set to 0.
Page 261 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) Fig 44. USART block diagram UM10850 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved. User manual Rev. 2.4 — 13 September 2016...
Page 262 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) 21.6 Register description The reset value reflects the data stored in used bits only. It does not include the content of reserved bits. Table 306: Register overview: USART (base address 0x4008 4000 (USART0), 0x4008 8000 (USART1), 0x4008 C000...
Page 263 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) 21.6.1 USART Configuration register The CFG register contains communication and mode settings for aspects of the USART that would normally be configured once in an application. Remark: Only the CFG register can be written when the ENABLE bit = 0. CFG can be set up by software with ENABLE = 1, then the rest of the USART can be configured.
Page 264 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) Table 307. USART Configuration register (CFG, offset 0x00) bit description …continued Symbol Value Description Reset Value LINMODE LIN break mode enable. Disabled. Break detect and generate is configured for normal operation. Enabled. Break detect and generate is configured for LIN bus operation.
Page 265 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) Table 307. USART Configuration register (CFG, offset 0x00) bit description …continued Symbol Value Description Reset Value OEPOL Output Enable Polarity. Low. If selected by OESEL, the output enable is active low. High. If selected by OESEL, the output enable is active high.
Page 266 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) 21.6.2 USART Control register The CTL register controls aspects of USART operation that are more likely to change during operation. Table 308. USART Control register (CTL, offset 0x04) bit description Symbol Value Description...
Page 267 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) 21.6.3 USART Status register The STAT register primarily provides a complete set of USART status flags for software to read. Flags other than read-only flags may be cleared by writing ones to corresponding bits of STAT.
Page 268 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) Table 309. USART Status register (STAT, offset 0x08) bit description Symbol Description Reset Access value PARITYERRINT Parity Error interrupt flag. This flag is set when a parity error is detected in a received character.
Page 269 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) Table 310. USART Interrupt Enable read and set register (INTENSET, offset 0x0C) bit description …continued Symbol Description Reset Value RXNOISEEN When 1, enables an interrupt when noise is detected. See description of the...
Page 270 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) 21.6.7 USART Receiver Data with Status register The RXDATSTAT register contains the next complete character to be read and its relevant status flags. This allows getting all information related to a received character with one 16-bit read, which may be especially useful when the DMA is used with the USART receiver.
Page 271 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) 21.6.9 USART Baud Rate Generator register The Baud Rate Generator is a simple 16-bit integer divider controlled by the BRG register. The BRG register contains the value used to divide the base clock in order to produce the clock used for USART internal operations.
Page 272 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) 21.6.10 USART Interrupt Status register The read-only INTSTAT register provides a view of those interrupt flags that are currently enabled. This can simplify software handling of interrupts. See Table 309 for detailed descriptions of the interrupt flags.
Page 273 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) 21.6.12 Address register The ADDR register holds the address for hardware address matching in address detect mode with automatic address matching enabled. Table 318. Address register (ADDR, offset 0x2C) bit description Symbol...
Page 274 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) 21.7 Functional description 21.7.1 Clocking and baud rates In order to use the USART, clocking details must be defined such as setting up the BRG, and typically also setting up the FRG. See Figure 21.7.1.1 Fractional Rate Generator (FRG)
Page 275 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) data bit must be reduced to one. Finally, special clocking has to be used for individual bit times because 32 kHz is not particularly close to an even multiple of any standard baud rate.
Page 276 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) Fig 45. Hardware flow control using RTS and CTS 21.7.4.2 Software flow control Software flow control could include XON / XOFF flow control, or other mechanisms. these are supported by the ability to check the current state of the CTS input, and/or have an...
Page 277 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) Automatic data direction control with the RTS pin can be set up using the OESEL, OEPOL, and OETA bits in the CFG register (Section 21.6.1). Data direction control can also be implemented in software using a GPIO pin.
Page 278 UM10850 NXP Semiconductors Chapter 21: LPC5410x USARTs (USART0/1/2/3) As a LIN slave, the autobaud feature can be used to synchronize to a LIN sync byte, and will return the value of the sync byte as confirmation of success. Wake-up for LIN can potentially be handled in a number of ways, depending on the system, and what clocks may be running in a slave device.
Page 279 UM10850 Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) Rev. 2.4 — 13 September 2016 User manual 22.1 How to read this chapter SPI0 and SPI1 are available on all parts. 22.2 Features • Data transmits of 1 to 16 bits supported directly. Larger frames supported by software.
Page 280 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) In Deep-sleep or Power-down mode, the SPI clock is turned off as are all peripheral clocks. However, if the SPI is configured in slave mode and an external master on the provides the clock signal, the SPI can create an interrupt asynchronously.
Page 281 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) 22.4 Pin description The SPI signals are movable functions and are assigned to external pins via IOCON. See Chapter 7. Recommended IOCON settings are shown in Table 320. Table 319: SPI Pin Description...
Page 282 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) Table 320: Suggested SPI pin settings IOCON Type D pin Type A pin Type I pin bit(s) MODE: Set to 00 (pull-down/pull-up resistor not enabled). Same as type D. Not used, set to 0.
Page 283 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) 22.6 Register description The Reset Value reflects the data stored in used bits only. It does not include reserved bits content. Table 321. Register overview: SPI (base address 0x400A 4000 (SPI0) and 0x400A 8000 (SPI1))
Page 284 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) Table 322. SPI Configuration register (CFG, offset 0x00) bit description …continued Symbol Value Description Reset value LSBF LSB First mode enable. Standard. Data is transmitted and received in standard MSB first order.
Page 285 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) 22.6.2 SPI Delay register The DLY register controls several programmable delays related to SPI signalling. These delays apply only to master mode, and are all stated in SPI clocks. Timing details are shown in: Section 22.7.2.1 “Pre_delay and Post_delay”...
Page 286 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) 22.6.3 SPI Status register The STAT register provides SPI status flags for software to read, and a control bit for forcing an end of transfer. Flags other than read-only flags may be cleared by writing ones to corresponding bits of STAT.
Page 287 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) 22.6.4 SPI Interrupt Enable read and Set register The INTENSET register is used to enable various SPI interrupt sources. Enable bits in INTENSET are mapped in locations that correspond to the flags in the STAT register. The complete set of interrupt enables may be read from this register.
Page 288 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) Table 325. SPI Interrupt Enable read and Set register (INTENSET, offset 0x0C) bit description Symbol Value Description Reset value MSTIDLEEN Master idle interrupt enable. No interrupt will be generated when the SPI master function is idle.
Page 289 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) 22.6.6 SPI Receiver Data register The read-only RXDAT register provides the means to read the most recently received data. The value of SSEL can be read along with the data.
Page 290 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) 22.6.7 SPI Transmitter Data and Control register The TXDATCTL register provides a location where both transmit data and control information can be written simultaneously. This allows detailed control of the SPI without a...
Page 291 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) Table 328. SPI Transmitter Data and Control register (TXDATCTL, offset 0x18) bit description …continued Symbol Value Description Reset value TXSSEL3_N Transmit Slave Select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default.
Page 292 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) 22.6.8 SPI Transmitter Data Register The TXDAT register is written in order to send data via the SPI transmitter when control information is not changing during the transfer (see Section 22.6.7).
Page 293 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) 22.6.10 SPI Divider register The DIV register determines the clock used by the SPI in master mode. For details on clocking, see Section 22.7.3 “Clocking and data rates”. Table 331. SPI Divider register (DIV, offset 0x24) bit description...
Page 294 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) 22.7 Functional description 22.7.1 Operating modes: clock and phase selection SPI interfaces typically allow configuration of clock phase and polarity. These are sometimes referred to as numbered SPI modes, as described in...
Page 295 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) 22.7.2 Frame delays Several delays can be specified for SPI frames. These include: • Pre_delay: delay after SSEL is asserted before data clocking begins • Post_delay: delay at the end of a data frame before SSEL is deasserted •...
Page 296 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) 22.7.2.2 Frame_delay The Frame_delay value controls the amount of time at the end of each frame. This delay is inserted when the EOF bit = 1. Frame_delay is illustrated by the examples in Figure Note that frame boundaries occur only where specified.
Page 297 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) 22.7.2.3 Transfer_delay The Transfer_delay value controls the minimum amount of time that SSEL is deasserted between transfers, because the EOT bit = 1. When Transfer_delay = 0, SSEL may be deasserted for a minimum of one SPI clock time.
Page 298 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) 22.7.3 Clocking and data rates In order to use the SPI, clocking details must be defined. This includes configuring the system clock and selection of the clock divider value in DIV. See Figure 3 “Clock...
Page 299 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) 22.7.5 DMA operation A DMA request is provided for each SPI direction, and can be used in lieu of interrupts for transferring data by configuring the DMA controller appropriately. The DMA controller provides an acknowledgement signal that clears the related request when it completes handling that request.
Page 300 UM10850 NXP Semiconductors Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1) A stall for Master receive can happen when a receiver overrun would otherwise occur if the transmitter was not stalled. In modes 0 and 2, this occurs if the previously received data is not read before the end of the next piece of is received.
Page 301 UM10850 Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) Rev. 2.4 — 13 September 2016 User manual 23.1 How to read this chapter C-bus interfaces are available on all parts. Read this chapter to understand the I C operation, software interface, and how to use the C for wake-up from reduced power modes.
Page 302 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) 23.3 Pin description The I C pins are fixed-pin functions and enabled through IOCON. Refer to the IOCON settings table for I C modes in Section 7.5.2. Table 334. I C-bus pin description...
Page 303 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) 23.4.1.1 Master write to slave Configure I2C0 as a master: Set the MSTEN bit to 1 in the CFG register. See Table 342. Write data to the slave: 1. Write the slave address with the RW bit set to 0 to the Master data register MSTDAT.
Page 304 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) 23.4.1.2 Master read from slave Configure I2C0 as a master: Set the MSTEN bit to 1 in the CFG register. See Table 342. Read data from the slave: 1. Write the slave address with the RW bit set to 1 to the Master data register MSTDAT.
Page 305 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) 23.4.2.1 Slave read from master Configure I2C0 as slave with address x: • Set the SLVEN bit to 1 in the CFG register. See Table 342. • Write the slave address x to the address 0 match register. See Table 368.
Page 306 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) 23.4.2.2 Slave write to master • Set the SLVEN bit to 1 in the CFG register. See Table 342. • Write the slave address x to the address 0 match register. See Table 368.
Page 307 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) – Start/stop error – Slave pending – Address match (in slave mode) – Data available/ready 23.4.3.2 Wake-up from Deep-sleep and Power-down modes • Enable the I C interrupt in the NVIC.
Page 308 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) 23.6 Register description The base addresses of the I C blocks are: Table 339. I C base addresses I2C block Base address I2C0 0x4009 4000 I2C1 0x4009 8000 I2C2 0x4009 C000 The register functions can be grouped as follows: •...
Page 309 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) Table 340: Register overview: I2C0/1/2 (register base addresses 0x4009 4000 (I2C0), 0x4009 8000 (I2C1), 0x4009 C000 (I2C2)) Name Access Offset Description Reset Reference value 0x00 Configuration for shared functions. Table 342...
Page 310 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) 23.6.1 I2C Configuration register The CFG register contains mode settings that apply to Master, Slave, and Monitor functions. Table 341. Address map CFG register Peripheral Base address Offset Increment Dimension I2C0...
Page 311 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) Table 342. I2C Configuration register (CFG, address offset 0x000) bit description Symbol Value Description Reset Value HSCAPABLE High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I C signalling, enabling High-speed mode applies to all functions: master, slave, and monitor.
Page 312 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) 23.6.2 I2C Status register The STAT register provides status flags and state information about all of the functions of the I C block. Access to bits in this register varies. RO = Read-only, W1 = write 1 to clear.
Page 313 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) Table 344. I C Status register (STAT, address offset 0x004) bit description …continued Symbol Value Description Reset Access value Master Start/Stop Error flag. This flag can be cleared by software writing a 1 STSTPERR to this bit.
Page 314 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) Table 344. I C Status register (STAT, address offset 0x004) bit description …continued Symbol Value Description Reset Access value 13:12 SLVIDX Slave address match Index. This field is valid when the I...
Page 315 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) Table 344. I C Status register (STAT, address offset 0x004) bit description …continued Symbol Value Description Reset Access value 23:20 - Reserved. Read value is undefined, only zero should be written.
Page 316 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) 23.6.3 Interrupt Enable Set and read register The INTENSET register controls which I C status flags generate interrupts. Writing a 1 to a bit position in this register enables an interrupt in the corresponding position in the STAT...
Page 317 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) Table 348. Interrupt Enable Set and read register (INTENSET, address offset 0x008) bit description Symbol Value Description Reset value MONIDLEEN Monitor Idle interrupt Enable. Disabled. The MonIdle interrupt is disabled. Enabled. The MonIdle interrupt is enabled.
Page 318 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) Table 350. Interrupt Enable Clear register (INTENCLR, address offset 0x00C) bit description …continued Symbol Description Reset value 23:20 - Reserved. Read value is undefined, only zero should be written. EVENTTIMEOUTCLR Event time-out interrupt clear.
Page 319 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) 23.6.6 Clock Divider register The CLKDIV register divides down the Peripheral Clock (PCLK) to produce the I function clock that is used to time various aspects of the I C interface. The I...
Page 320 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) Table 356. I C Interrupt Status register (INTSTAT, address offset 0x018) bit description Symbol Description Reset value 10:9 Reserved. Read value is undefined, only zero should be written. SLVNOTSTR Slave Not Stretching status.
Page 321 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) 23.6.8 Master Control register The MSTCTL register contains bits that control various functions of the I C Master interface. Only write to this register when the master is pending (MSTPENDING = 1 in the...
Page 322 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) Table 358. Master Control register (MSTCTL, address offset 0x020) bit description Symbol Value Description Reset value MSTDMA Master DMA enable. Data operations of the I C can be performed with DMA.
Page 323 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) Table 360. Master Time register (MSTTIME, address offset 0x024) bit description …continued Symbol Value Description Reset value MSTSCLHIGH Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL.
Page 324 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) 23.6.11 Slave Control register The SLVCTL register contains bits that control various functions of the I C Slave interface. Only write to this register when the slave is pending (SLVPENDING = 1 in the STAT...
Page 325 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) Table 366. Slave Data register (SLVDAT, address offset 0x044) bit description Symbol Description Reset Value DATA Slave function data register. Read: read the most recently received data for the Slave function.
Page 326 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) Table 370. Slave address Qualifier 0 register (SLVQUAL0, address offset 0x058) bit description Symbol Value Description Reset Value QUALMODE0 Qualify mode for slave address 0. Mask. The SLVQUAL0 field is used as a logical mask for matching address 0.
Page 327 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) 23.6.15 Monitor data register The read-only MONRXDAT register provides information about events on the I C bus, primarily to facilitate debugging of the I C during application development. All data addresses and data passing on the bus and whether these were acknowledged, as well as Start and Stop events, are reported.
Page 328 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) 23.7 Functional description 23.7.1 Bus rates and timing considerations Due to the nature of the I C bus, it is generally not possible to guarantee a specific clock rate on the SCL pin. On the I C-bus, the clock can be stretched by any slave device, extended by software overhead time, etc.
Page 329 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) The I C interface supports Standard-mode, Fast-mode, and Fast-mode Plus with the same software sequence, which also supports SMBus. High-speed mode is intrinsically incompatible with SMBus due to conflicting requirements and limitations for clock stretching, and therefore requires a slightly different software sequence.
Page 330 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) – as a slave transmitter, after each after each data byte is sent and the matching acknowledge is received from the master In each case, the relevant pending flag (MSTPENDING or SLVPENDING) is set at the point where clock stretching occurs.
Page 331 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) For Slave Transmitter mode, the slave function responds to the initial address in the same fashion as for Slave Receiver mode, and checks that it has previously been addressed with a full 10-bit address. If the address matched is address 0, and address qualification is enabled, software must check that the first part of the 10-bit address is a complete match to the previous address before acknowledging the address.
Page 332 UM10850 NXP Semiconductors Chapter 23: LPC5410x I2C-bus interfaces (I2C0/1/2) 23.7.6.2 DMA as a Master receiver A basic sequence for a Master receiver: • Software sets up DMA to receive a message. • Software causes a slave address with read command to be sent and checks that the address was acknowledged.
Page 333 UM10850 Chapter 24: LPC5410x System FIFO for Serial Peripherals Rev. 2.4 — 13 September 2016 User manual 24.1 How to read this chapter Read this chapter for a description of the optional FIFOs for the USART and SPI interfaces. 24.2 Basic configuration The System FIFO is configured using the following registers: •...
Page 334 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals • A receiver timeout feature (for USART and SPI) provides a means to get data left for a time in a FIFO that has not reached its threshold to be transferred.
Page 335 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals 24.4 Architecture The architecture of the System FIFO is shown in Figure 53. System connection for the FIFO are shown in Figure Fig 53. System FIFO conceptual block diagram Fig 54.
Page 336 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals 24.5 Register description Table 373. Register overview: FIFO register map (base address 0x1C03 8000) Name Access Address Description Reset Refer- Offset Value ence Global System FIFO registers FIFOCTLUSART 0x0100 USART FIFO global control register.
Page 337 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals Table 373. Register overview: FIFO register map (base address 0x1C03 8000) Name Access Address Description Reset Refer- Offset Value ence CFGUSART2 0x1200 USART2 configuration STATUSART2 0x1204 USART2 status 0x300...
Page 338 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals Table 373. Register overview: FIFO register map (base address 0x1C03 8000) Name Access Address Description Reset Refer- Offset Value ence CTLCLRSPI1 0x2110 SPI1 control clear register. Writing a 1 to any implemented bit position causes the corresponding bit in the related CTLSET register to be cleared.
Page 339 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals 24.5.1 USART FIFO global control register The FIFOCTLUSART register contains information about the configuration of USART support for the specific instance of the System FIFO as well as global control and status for the USART FIFOs.
Page 340 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals Table 375. USART FIFO global reset register (FIFOUPDATEUSART, address offset 0x0104) bit description Symbol Description Reset Value USART2TX Writing 1 updates USART2 Tx FIFO size to match the USART2 TXSIZE. Must be UPDATESIZE done for all USARTs when any USART TXSIZE is changed.
Page 341 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals 24.5.4 SPI FIFO global control register The FIFOCTLSPI register contains information about the configuration of SPI support for the specific instance of the System FIFO as well as global control and status for the SPI FIFOs.
Page 342 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals 24.5.6 FIFO configuration register for SPI0 and SPI1 The FIFOCFGSPI register configure the FIFO sizes for the SPI receiver and related transmitter. Each SPI has a dedicated FIFOCFG register.
Page 343 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals 24.5.7 Configuration register for USARTn The CFGUSART register allows configuration of the transmit and receive FIFO thresholds and the receive FIFO timeout. Each USART has a dedicated CFGUSART register.
Page 344 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals For instance, if TimeoutBase is set to 5, then 4 bits of the timeout timer starting at bit 5 are compared to TimeoutValue. Since bit 5 changes every 32 counts of the timeout timer, the maximum time for a timeout to occur (since the timer may change immediately after data is entered into the FIFO) is TimeoutValue (a range of 2 to 15) * 32 clocks.
Page 345 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals 24.5.9 Interrupt status register for USARTn The read-only INTSTATUSART register provides information about a peripheral being serviced by the System FIFO that may be needed by an interrupt service routine. Each USART has a dedicated INTSTATUSART register.
Page 346 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals Table 389. Control read and set register for USARTn (CTLSETUSART[0:3], address offset [0x100C:0x130C]) bit description Symbol Description Reset Value RXTIMEOUT Receive FIFO Timeout Interrupt Enable. When enabled, this also enables the INTEN timeout for this USART.
Page 347 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals Table 393. Received data register for USARTn (RXDATUSART[0:3], address offset [0x1014:0x1314]) bit description Symbol Description Reset Value RXDAT The UART Receiver Data register contains the next received character. The number of bits that are relevant depends on the UART configuration settings.
Page 348 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals 24.5.15 Configuration register for SPI0 and SPI1 The CFGSPI register allows configuration of the transmit and receive FIFO thresholds and the receive FIFO timeout. Each SPI has a dedicated CFGSPI register.
Page 349 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals 24.5.15.1 Receiver Timeout A single 19-bit timeout timer is used for all receiver FIFOs. TimeoutBase chooses a bit of that timer to be used as the place to begin comparing the timer to TimeoutValue, from bit 0 up to bit 15.
Page 350 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals 24.5.17 Interrupt status register for SPI0 and SPI1 The read-only INTSTATSPI register provides information about a peripheral being serviced by the System FIFO that may be needed by an interrupt service routine. Each SPI has a dedicated INTSTATSPI register.
Page 351 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals Table 405. Control read and set register for SPIn (CTLSETSPI[0:1], address offset [0x200C:0x210C]) bit description Symbol Description Reset Value RXFLUSH Receive FIFO flush. Writing a 1 to this bit forces the receive FIFO to be empty.
Page 352 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals Table 409. Received data register for SPIn (RXDATSPI[0:1], address offset [0x2014:0x2114]) bit description Symbol Description Reset Value 15:0 RXDAT Receiver Data. This contains the next piece of received data. The number of bits that are used depends on the LEN setting in TXCTL / TXDATCTL.
Page 353 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals Table 411. Transmit data register for SPIn (TXDATCTLSPI[0:1], address offset [0x2018:0x2118]) bit description Symbol Description Reset Value 15:0 TXDAT Transmit Data. This field provides from 1 to 16 bits of data to be transmitted.
Page 354 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals Table 411. Transmit data register for SPIn (TXDATCTLSPI[0:1], address offset [0x2018:0x2118]) bit description Symbol Description Reset Value RXIGNORE Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver to simplify the transmit process and can be used with the DMA.
Page 355 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals 24.6 Operational details This section describes details of System FIFO operation. 24.6.1 Configuring peripheral FIFOs To configure a FIFO for use or re-configure a FIFO after prior use: 1. Pause the desired directions (transmit and/or receive) of the desired peripheral types (USART and/or SPI).
Page 356 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals When DMA is being used to receive data from the FIFO, the timeout has a limited value. A DMA request is always generated whenever the FIFO is not empty, so there should never be idle data in the FIFO for any length of time.
Page 357 UM10850 NXP Semiconductors Chapter 24: LPC5410x System FIFO for Serial Peripherals 24.7 Generic FIFO setup Before the FIFOs can be used, they require some basic setup. 24.7.1 System FIFO activation • Write 0x200 to AHB_CLK_CTRLSET1 in Syscon, enabling the clock to the FIFOs.
Page 358 UM10850 Chapter 25: LPC5410x 12-bit ADC controller (ADC0) Rev. 2.4 — 13 September 2016 User manual 25.1 How to read this chapter The ADC controller is available on all parts. The number of ADC channels available is dependent on the package size.
Page 359 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) been in a low-power sleep mode for a considerable period of time). Re-calibration should also be performed if the ADC clock rate is changed. To perform a calibration, use the ADC API.
Page 360 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.4 Pin description The ADC can measure the voltage on any of the input signals on the analog input channel. Digital signals must be disconnected from the ADC input pins when the ADC function is to be used by setting DIGIMODE = 0 on those pins in the related IOCON registers.
Page 361 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) Table 413. ADC0 pin description Function Connect to Description ADC0_6 PIO1_3 Analog input channel 6. ADC0_7 PIO1_4 Analog input channel 7. ADC0_8 PIO1_5 Analog input channel 8. ADC0_9 PIO1_6 Analog input channel 9.
Page 362 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.5 General description ADCn ADC0_PINTRIG1:0 sequence A/B start complete IRQ SCT0_OUTm conversion CONVERSION NVIC TRIGGER data overrun IRQ ARM_TXEV NVIC ANALOG-to- DIGITAL CONVERTER result CHANNEL channel DATA select REGISTERS SEQUENCE...
Page 363 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.6 Register description The reset value reflects the data stored in used bits only. It does not include reserved bits content. Table 415. Register overview: ADC (base address 0x1C03 4000)
Page 364 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) Table 415. Register overview: ADC (base address 0x1C03 4000) Name Access Address Description Reset Reference offset value THR1_LOW 0x054 ADC Low Compare Threshold Register 1: Contains the lower Table 424 threshold level for automatic threshold comparison for any channels linked to threshold pair 1.
Page 365 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.6.1 ADC Control Register This register specifies the clock divider value to be used to generate the ADC clock in synchronous mode and general operating mode bits including resolution and sampling time.
Page 366 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) Table 416. ADC Control Register (CTRL, address offset 0x0) bit description Symbol Value Description Reset value BYPASSCAL Bypass Calibration. This bit may be set to avoid the need to calibrate if offset error is not a concern in the application.
Page 367 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.6.2 ADC Conversion Sequence A Control Register There are two independent conversion sequences that can be configured, each consisting of a set of conversions on one or more channels. This control register specifies the channel selection and trigger conditions for the A sequence and contains bits to allow software to initiate that conversion sequence.
Page 368 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) Table 417: ADC Conversion Sequence A Control Register (SEQA_CTRL, address offset 0x08) bit description Symbol Value Description Reset value START Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger.
Page 369 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) Table 417: ADC Conversion Sequence A Control Register (SEQA_CTRL, address offset 0x08) bit description Symbol Value Description Reset value SEQA_ENA Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQA_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit).
Page 370 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.6.3 ADC Conversion Sequence B Control Register There are two independent conversion sequences that can be configured, each consisting of a set of conversions on one or more channels. This control register specifies the channel selection and trigger conditions for the B sequence, as well bits to allow software to initiate that conversion sequence.
Page 371 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) Table 418: ADC Conversion Sequence B Control Register (SEQB_CTRL, address offset 0x0C) bit description Symbol Value Description Reset value START Writing a 1 to this field will launch one pass through this conversion sequence. The behavior will be identical to a sequence triggered by a hardware trigger.
Page 372 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.6.4 ADC Global Data Register A and B The ADC Global Data Registers contain the result of the most recent ADC conversion completed under each conversion sequence. Results of ADC conversions can be read in one of two ways. One is to use these ADC Global Data Registers to read data from the ADC at the end of each ADC conversion.
Page 373 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) Table 420: ADC Sequence B Global Data Register (SEQB_GDAT, address offset 0x14) bit description Symbol Description Reset value Reserved. 15:4 RESULT This field contains the 12-bit ADC conversion result from the most recent conversion performed under conversion sequence associated with this register.
Page 374 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.6.5 ADC Channel Data Registers 0 to 11 The ADC Channel Data Registers hold the result of the last conversion completed for each ADC channel. They also include status bits to indicate when a conversion has been completed, when a data overrun has occurred, and where the most recent conversion fits relative to the range dictated by the high and low threshold registers.
Page 375 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) Table 422. ADC Data Registers (DAT[0:11], address offset [0x020:0x04C]) bit description Symbol Description Reset value 19:18 THCMP Threshold Crossing Comparison result. CROSS 0x0 = No threshold Crossing detected: The most recent completed conversion on this channel had the same relationship (above or below) to the threshold value established by the designated LOW threshold register (THRn_LOW) as did the previous conversion on this channel.
Page 376 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.6.6 ADC Compare Low Threshold Registers 0 and 1 These registers set the LOW threshold levels against which ADC conversions on all channels will be compared. Each channel will either be compared to the THR0_LOW/HIGH registers or to the THR1_LOW/HIGH registers depending on what is specified for that channel in the CHAN_THRSEL register.
Page 377 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.6.7 ADC Compare High Threshold Registers 0 and 1 These registers set the HIGH threshold level against which ADC conversions on all channels will be compared. Each channel will either be compared to the THR0_LOW/HIGH registers or to the THR1_LOW/HIGH registers depending on what is specified for that channel in the CHAN_THRSEL register.
Page 378 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.6.8 ADC Channel Threshold Select register For each channel, this register indicates which pair of threshold registers conversion results should be compared to. Table 427: ADC Channel Threshold Select register (CHAN_THRSEL, address offset 0x60) bit description...
Page 379 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.6.9 ADC Interrupt Enable Register There are four separate interrupt requests generated by the ADC: conversion, these are -complete or sequence-complete interrupts for each of the two sequences, a threshold-comparison out-of-range interrupt, and a data overrun interrupt. The two conversion/sequence-complete interrupts can also serve as DMA triggers.
Page 380 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) Table 428: ADC Interrupt Enable register (INTEN, address offset 0x64) bit description Symbol Value Description Reset value ADCMPINTEN0 Threshold comparison interrupt enable for channel 0. Disabled. Outside threshold. Crossing threshold.
Page 381 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.6.10 ADC Flags register The ADC Flags registers contains the four interrupt/DMA trigger flags along with the individual overrun flags that contribute to an overrun interrupt and the component threshold-comparison flags that contribute to that interrupt. Note that the threshold and overrun interrupts hare a slot in the NVIC.
Page 382 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) Table 429: ADC Flags register (FLAGS, address offset 0x68) bit description Symbol Description Reset value SEQA_INT Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every ADC conversion performed as part of sequence A.
Page 383 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.6.11 ADC Startup register This register is used exclusively when enabling the ADC, and typically only by the ADC API. This register should never be accessed during normal ADC operation. The ADC clock should be selected and running at full frequency prior to writing to this register.
Page 384 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.7 Functional description 25.7.1 Conversion Sequences A conversion sequence is a single pass through a series of ADC conversions performed on a selected set of ADC channels. Software can configure up to two independent conversion sequences, either of which can be triggered by software or by a transition on one of the hardware triggers.
Page 385 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.7.2.1 Avoiding spurious hardware triggers Care should be taken to avoid generating a spurious trigger when writing to the SEQn_CTRL register to change the trigger selected for the sequence, switch the polarity of the selected trigger, or to enable the sequence for operation.
Page 386 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) If the MODE bit for the sequence is 1 (sequence-complete mode) then the interrupt flag/DMA request must be written-to by software to clear it (except when used as a DMA trigger, in which case it will be cleared in hardware by the DMA engine).
Page 387 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.7.6 Offset calibration and enabling the ADC The A/D converter includes a built-in, self-calibration mode which can be used to minimize offset error. For applications where offset error is not a concern, calibration may be disabled by setting the BYPASSCAL bit in the CTRL register.
Page 388 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) For DMA transfers, only burst requests are supported. The burst size can be set to one in the DMA channel control register. If the number of ADC channels is not equal to one of the other DMA-supported burst sizes (applicable DMA burst sizes are 1, 4, 8), set the burst size to one.
Page 389 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) Table 433. Minimum required sample times Selected ADC Analog signal Fast channels (ADC5:0) Slow channels (ADC11:6) Resolution source impedance Min. sample time TSAMP field Min. sample time TSAMP field 12 bits under 0.05k ohms...
Page 390 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.8 Examples 25.8.1 Perform a single ADC conversion triggered by software Remark: When ADC conversions are triggered by software only and hardware triggers are not used in the conversion sequence, follow these steps to avoid spurious conversions: 1.
Page 391 UM10850 NXP Semiconductors Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.8.2 Perform a sequence of conversions triggered by an external pin The ADC can perform conversions on a sequence of selected channels. Each individual conversion of the sequence (single-step) or the entire sequence can be triggered by hardware.
Page 392 Chapter 26: LPC5410x CRC engine Rev. 2.4 — 13 September 2016 User manual 26.1 How to read this chapter The CRC engine is available on all LPC5410x parts. 26.2 Features • Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32. – CRC-CCITT: x –...
Page 393 UM10850 NXP Semiconductors Chapter 26: LPC5410x CRC engine 26.5 General description The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. Fig 58. CRC block diagram UM10850 All information provided in this document is subject to legal disclaimers.
Page 394 UM10850 NXP Semiconductors Chapter 26: LPC5410x CRC engine 26.6 Register description Table 434. Register overview: CRC engine (base address 0x1C01 0000) Name Access Address Description Reset value Reference offset MODE 0x000 CRC mode register 0x0000 0000 Table 435 SEED 0x004...
Page 395 UM10850 NXP Semiconductors Chapter 26: LPC5410x CRC engine 26.6.3 CRC checksum register This register is a Read-only register containing the most recent checksum. The read request to this register is automatically delayed by a finite number of wait states until the results are valid and the checksum computation is complete.
Page 396 UM10850 NXP Semiconductors Chapter 26: LPC5410x CRC engine 26.7 Functional description The following sections describe the register settings for each supported CRC standard: 26.7.1 CRC-CCITT set-up Polynomial = x Seed Value = 0xFFFF Bit order reverse for data input: NO...
Page 397 Chapter 27: LPC5410x Mailbox Rev. 2.4 — 13 September 2016 User manual 27.1 How to read this chapter The Mailbox is available on all LPC5410x parts. 27.2 Features • Provides a means Inter-Processor Communication, allowing multiple CPUs to share resources and communicate with each other in a simple manner.
Page 398 UM10850 NXP Semiconductors Chapter 27: LPC5410x Mailbox 27.6 Register description Table 439. Register overview: Mailbox (base address 0x1C02 C000) Name Access Address Description Reset value Reference offset IRQ0 0x000 Interrupt request register for the Cortex-M0+ CPU. Table 440 IRQ0SET 0x004...
Page 399 UM10850 NXP Semiconductors Chapter 27: LPC5410x Mailbox 27.6.4 M4 interrupt register The IRQ1 register allows other CPUs to send interrupt requests to the Cortex-M4 CPU. This is intended to allow communication between CPUs. For example, one CPU could be handling certain peripherals and signalling another CPU when data is available Each bit can represent a different situation.
Page 400 UM10850 Chapter 28: LPC5410x Flash signature generator Rev. 2.4 — 13 September 2016 User manual 28.1 How to read this chapter The flash signature generator is present on all LPC5410x devices. 28.2 Features • Controls hardware flash signature generation. •...
Page 401 UM10850 NXP Semiconductors Chapter 28: LPC5410x Flash signature generator 28.4 Register description Remark: To configure flash access times, use the FLASHCFG register in the SYSCON block. See Section 4.5.33. Table 447. Register overview: FMC (base address 0x4002 4000) Name Access...
Page 402 UM10850 NXP Semiconductors Chapter 28: LPC5410x Flash signature generator 28.4.2 Signature generation result registers The signature generation result registers return the flash signature produced by the embedded signature generator. The 128-bit signature is reflected by the four registers FMSW0, FMSW1, FMSW2 and FMSW3.
Page 403 UM10850 NXP Semiconductors Chapter 28: LPC5410x Flash signature generator Table 455. Signature status clear register (FMSTATCLR, offset 0x0FE8) bit description Symbol Description Reset value Reserved. Read value is undefined, only zero should be written. SIG_DONE_CLR Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register.
Page 404 UM10850 Chapter 29: LPC5410x Serial Wire Debug (SWD) Rev. 2.4 — 13 September 2016 User manual 29.1 How to read this chapter Debug functionality is available on all parts. Details depend on whether the Cortex-M0+ is present on the device.
Page 405 UM10850 NXP Semiconductors Chapter 29: LPC5410x Serial Wire Debug (SWD) The JTAG boundary pin functions are selected by hardware at reset. See Section 29.6.3. The following setup is required to enable SWO output on GPIO PIO0-15 (FUNC2) or PIO1_1 (FUNC2): 1.
Page 406 UM10850 NXP Semiconductors Chapter 29: LPC5410x Serial Wire Debug (SWD) 29.5 General description Serial wire debug functions are integrated into each CPU, with up to four breakpoints and two watchpoints. Boundary scan is also available. Trace on the Cortex-M4 is supported via the Serial Wire Output.
Page 407 UM10850 NXP Semiconductors Chapter 29: LPC5410x Serial Wire Debug (SWD) Fig 59. Connecting the SWD pins to a standard SWD connector Fig 60. Serial Wire Debug internal connections UM10850 All information provided in this document is subject to legal disclaimers.
Page 408 UM10850 NXP Semiconductors Chapter 29: LPC5410x Serial Wire Debug (SWD) 29.6.3 Boundary scan The RESET pin selects between the test TAP controller for JTAG boundary scan (RESET = LOW) and the ARM SWD debug port TAP controller (RESET = HIGH). The ARM SWD debug port is disabled while the part is in reset.
Page 409 UM10850 NXP Semiconductors Chapter 29: LPC5410x Serial Wire Debug (SWD) Table 458. Register overview: ISP-AP (base address 0x1C04 0000) Name Access Address Description Reset value Reference offset 0x00 Command and status word. Table 459 REQUEST R/W 0x04 Request from the debugger to the device.
Page 410 UM10850 NXP Semiconductors Chapter 29: LPC5410x Serial Wire Debug (SWD) 29.6.4.5.4 Identification register (ID, offset 0xFC) bit description The ID register provides an identification of the ISP-AP interface. Table 462. Identification register (ID, offset 0xFC) bit description Symbol Description Reset value 31:0 Identification value.
Page 411 Rev. 2.4 — 13 September 2016 User manual 30.1 How to read this chapter The power profiles are available for all LPC5410x parts. The Power profiles and Power control APIs can be implemented using the power library from LPCOpen software package.
Page 412 UM10850 NXP Semiconductors Chapter 30: LPC5410x Power profiles/Power control API Fig 61. ROM power API pointer structure 30.4 API description Power APIs provide functions to configure the system clock and set up the system for expected performance requirements. The Power APIs are available in the power library provided with LPCOpen software package.
Page 413 UM10850 NXP Semiconductors Chapter 30: LPC5410x Power profiles/Power control API #define rom_driver_ptr (*(ROM) **) 0x0300 0200) pPWRD = (PWRD *)(rom_driver_ptr->pPWRD); Table 466. Power API calls in LPCOpen power library Function prototype API description Section Power API PLL configuration routine.This API sets up basic PLL operation.
Page 414 UM10850 NXP Semiconductors Chapter 30: LPC5410x Power profiles/Power control API 30.4.2 Chip_POWER_SetVoltage This routine configures the device’s internal power control settings according to the calling arguments. The goal is to prepare on-chip regulators to deliver the amount of power needed for the requested performance level, as defined by the CPU operating frequency.
Page 415 UM10850 NXP Semiconductors Chapter 30: LPC5410x Power profiles/Power control API Remark: Aside from the analog peripherals listed with this parameter, the serial peripherals can also wake up the chip from deep-sleep or power-down modes on an interrupt triggered by an incoming signal. This wake-up scenario is not configured using the Chip_POWER_EnterPowerMode API.
Page 416 31.3.7. 31.3.3 Flash content protection mechanism The LPC5410x is equipped with the Error Correction Code (ECC) capable Flash memory. The purpose of an error correction module is twofold. Firstly, it decodes data words read from the memory into output data words. Secondly, it encodes data words to be written to the memory.
Page 417 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API The operation of ECC is transparent to the running application. The ECC content itself is stored in a flash memory not accessible by user’s code to either read from it or write into it on its own.
Page 418 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API Section 31.5 “USART ISP commands” on page 423. 31.3.5 Flash partitions Some IAP and ISP commands operate on sectors and specify sector numbers. In addition, a page erase command is available. The size of a sector is 32 KB and the size of a page is 256 Byte.
Page 419 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API Table 474. Code Read Protection (CRP) options Name Pattern programmed Description in 0x0000 02FC NO_ISP 0x4E69 7370 Prevents sampling of the pin for entering ISP mode. ISP sampling pin is available for other applications.
Page 420 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API Table 475. ISP commands allowed for different CRP levels ISP command CRP1 CRP2 CRP3 (no entry in ISP mode allowed) Read Part ID Read Boot code version Compare ReadUID In case a CRP mode is enabled and access to the chip is allowed via the ISP, an unsupported or restricted ISP command will be terminated with return code CODE_READ_PROTECTION_ENABLED.
Page 421 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API 31.4 USART communication protocol All USART ISP commands should be sent as single ASCII strings. Strings should be terminated with Carriage Return (CR) and/or Line Feed (LF) control characters. Extra <CR> and <LF> characters are ignored. All ISP responses are sent as <CR><LF>...
Page 422 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API 31.5 USART ISP commands The following commands are accepted by the ISP command handler. Detailed status codes are supported for each command. The command handler sends the return code INVALID_COMMAND when an undefined command is received. Commands and return codes are in ASCII format.
Page 423 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API 31.5.2 Set Baud Rate Table 478. USART ISP Set Baud Rate command Command Input Baud Rate: 9600 | 19200 | 38400 | 57600 | 115200 Stop bit: 1 | 2 Return Code...
Page 424 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API 31.5.5 Read Memory Reads the plain binary code of the data stream, followed by the CMD_SUCCESS return code. Table 481. USART ISP Read Memory command Command Input Start Address: Address from where data bytes are to be read. This address should be a word boundary.
Page 425: Table Of Contents
UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API Remark: Once a page has been written to 16 times, it is still possible to write to other pages within the same sector without performing a sector erase (assuming that those pages have been erased previously).
Page 426 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API 31.5.9 Erase sectors Table 485. USART ISP Erase sector command Command Input Start Sector Number End Sector Number: Should be greater than or equal to start sector number. Return Code CMD_SUCCESS |...
Page 427: Return Code Cmd_Success
UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API 31.5.11 Blank check sectors Table 487. USART ISP Blank check sector command Command Input Start Sector Number: End Sector Number: Should be greater than or equal to start sector number. Return Code CMD_SUCCESS | SECTOR_NOT_BLANK (followed by <Offset of the first non blank word location>...
Page 428: Param_Error
UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API 31.5.14 Compare Table 491. USART ISP Compare command Command Input Address1 (DST): Starting flash or RAM address of data bytes to be compared. This address should be a word boundary. Address2 (SRC): Starting flash or RAM address of data bytes to be compared. This address should be a word boundary.
Page 429 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API Table 493. USART ISP Read CRC checksum command Command Input Address: The data are read from this address for CRC checksum calculation. This address must be on a word boundary. Number of Bytes: Number of bytes to be calculated for the CRC checksum; must be a multiple of 4.
Page 430 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API Table 495. USART ISP Error codes Return Error code Description Code ERR_ISP_DST_ADDR_NOT_MAPPED Destination address is not mapped in the memory map. Count value is taken in to consideration where applicable. ERR_ISP_COUNT_ERROR Byte count is not multiple of 4 or is not a permitted value.
Page 431 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API /*0x0000000C*/ ERR_ISP_PARAM_ERROR, /* Insufficient number of parameters */ /*0x0000000D*/ ERR_ISP_ADDR_ERROR, /* Address not on word boundary */ /*0x0000000E*/ ERR_ISP_ADDR_NOT_MAPPED, /*0x0000000F*/ ERR_ISP_CMD_LOCKED, /* Command is locked */ /*0x00000010*/ ERR_ISP_INVALID_CODE, /* Unlock code is invalid */...
Page 432 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API 31.6 IAP commands For in application programming the IAP routine should be called with a word pointer in register r0 pointing to memory (RAM) containing command code and parameters. The result of the IAP command is returned in the result table pointed to by register r1. The user can reuse the command table for result by passing the same pointer in registers r0 and r1.
Page 433 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API Up to 4 parameters can be passed in the r0, r1, r2 and r3 registers respectively (see the ARM Thumb Procedure Call Standard SWS ESPC 0002 A-05). Additional parameters are passed on the stack. Up to 4 parameters can be returned in the r0, r1, r2 and r3 registers respectively.
Page 434 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API 31.6.1 Prepare sector(s) for write operation This command makes flash write/erase operation a two step process. Table 497. IAP Prepare sector(s) for write operation command Command Prepare sector(s) for write operation Input...
Page 435 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API 31.6.3 Erase Sector(s) Table 499. IAP Erase Sector(s) command Command Erase Sector(s) Input Command code: 52 (decimal) Param0: Start Sector Number Param1: End Sector Number (should be greater than or equal to start sector number).
Page 436 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API 31.6.6 Read Boot code version number Table 502. IAP Read Boot Code version number command Command Read boot code version number Input Command code: 55 (decimal) Parameters: None Status code CMD_SUCCESS Result Result0: 2 bytes of boot code version number.
Page 437 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API 31.6.9 ReadUID Table 505. IAP ReadUID command Command Compare Input Command code: 58 (decimal) Status code CMD_SUCCESS Result Result0: The first 32-bit word (at the lowest address). Result1: The second 32-bit word.
Page 438 UM10850 NXP Semiconductors Chapter 31: LPC5410x Flash API 31.6.12 IAP Status Codes Table 508. IAP Status codes Summary Status Mnemonic Description code CMD_SUCCESS Command is executed successfully. INVALID_COMMAND Invalid command. SRC_ADDR_ERROR Source address is not on a word boundary. DST_ADDR_ERROR Destination address is not on a correct boundary.
Page 439 Chapter • Reset of the Cortex-M4 resets the CPU register bank. • Memory features: The memory map for LPC5410x devices is shown in Section 2.1.2. • Bit banding is included on the Cortex-M4. APB peripherals are located in bit-band space.
Page 440 • Sleep mode power-saving: NXP microcontrollers extend the number of reduced power modes beyond what is directly supported by the Cortex-M0+. Details of reduced power modes and wake-up possibilities on the LPC5410x can be found in Chapter • Reset of the Cortex-M0+ resets the CPU register bank.
Page 441 UM10850 Chapter 33: Supplementary information Rev. 2.4 — 13 September 2016 User manual 33.1 Abbreviations Table 509. Abbreviations Acronym Description Analog-to-Digital Converter Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Application Programming Interface BrownOut Detection BSDL Boundary-Scan Description Language Cyclic Redundancy Check Debug Communication Channel Direct Memory Access...
Page 442 UM10850 NXP Semiconductors Chapter 33: Supplementary information Cortex-M0+ TRM — ARM Cortex-M0+ Processor Technical Reference Manual AN11538 — AN11538 application note and code bundle (SCT cookbook) UM10850 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2016. All rights reserved.
Page 443 In no event shall NXP Semiconductors, its affiliates or their suppliers be liable use of such information. to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business 33.3.2 Disclaimers...
Page 444 UM10850 NXP Semiconductors Chapter 33: Supplementary information 33.4 Tables Table 1. Main SRAM configuration ....11 description ......36 Table 2.
Page 445 UM10850 NXP Semiconductors Chapter 33: Supplementary information Table 60. CLKOUT clock divider register (CLKOUTDIV, 0x4000 03F8) bit description ....62 address 0x4000 010C) bit description ..44 Table 87.
Page 446 UM10850 NXP Semiconductors Chapter 33: Supplementary information Table 115. Address map PIO0_[29:31] registers ..95 Table 147. Address map SET[0:1] registers ..111 Table 116. Type A IOCON registers(PIO0_[29:31], address Table 148.
Page 447 UM10850 NXP Semiconductors Chapter 33: Supplementary information 0x4001 4000 (GINT1)) bit description..141 Table 201. Address map CTLSTAT[0:21] registers..162 Table 173. GPIO grouped interrupt port polarity registers Table 202. Channel control and status registers bit (PORT_POL[0:1], addresses 0x4001 0020 description .
Page 448 UM10850 NXP Semiconductors Chapter 33: Supplementary information Table 260. Address map EMR register ....214 Table 231. SCT match reload registers 0 to 12 Table 261. Timer external match registers (EMR, address (MATCHREL[0:12], address 0x5000 4200 offset 0x03C) bit description .
Page 449 UM10850 NXP Semiconductors Chapter 33: Supplementary information address 0x4007 0000) bit description..246 Table 318. Address register (ADDR, offset 0x2C) bit Table 290. RI Mask LSB register (MASK, address description ......274 0x4007 0004) bit description .
Page 450 UM10850 NXP Semiconductors Chapter 33: Supplementary information Table 354. I C Clock Divider register (CLKDIV, offset 0x14) Table 386. Address map INTSTATUSART[0:3] registers 346 bit description ......320 Table 387.
Page 451 0x1C01 0008) bit description ... . .396 Table 472. LPC5410x flash configurations ... 417 Table 439. Register overview: Mailbox (base address Table 473.
Page 452 UM10850 NXP Semiconductors Chapter 33: Supplementary information Table 484. USART ISP Go command ....426 Table 485. USART ISP Erase sector command ..427 Table 486.
Page 453 UM10850 NXP Semiconductors Chapter 33: Supplementary information 33.5 Figures Fig 1. Block diagram ......9 Fig 46.
Page 454 SRAM usage notes..... 11 Chapter 3: LPC5410x Nested Vectored Interrupt Controller (NVIC) How to read this chapter ....15 3.4.10...
Page 455 Pin description ......85 Chapter 7: LPC5410x I/O pin configuration (IOCON) How to read this chapter ....87 Basic configuration.
Page 456 9.5.6 GPIO masked port pin registers ..111 Chapter 10: LPC5410x Pin interrupt and pattern match (PINT) 10.1 How to read this chapter ....116 10.6.5...
Page 457 NXP Semiconductors Chapter 33: Supplementary information Chapter 11: LPC5410x Group GPIO input interrupt (GINT0/1) 11.1 Features ......139 11.4.1...
Page 458 14.7.2 Timer Control Register ....209 Chapter 15: LPC5410x Windowed Watchdog Timer (WWDT) 15.1 How to read this chapter ....221 15.5.3.2...
Page 459 18.5.2 RI Mask LSB register ....246 Chapter 19: LPC5410x CPU system tick timer (SYSTICK) 19.1 How to read this chapter ....249 19.5.3...
Page 460 23.6.8 Master Control register ....322 Chapter 24: LPC5410x System FIFO for Serial Peripherals 24.1 How to read this chapter ....334 24.5.5...
Page 461 24.6 Operational details..... 356 Chapter 25: LPC5410x 12-bit ADC controller (ADC0) 25.1 How to read this chapter ....359 25.6.12...
Page 462 28.4.1.2 Flash signature stop address register..402 Chapter 29: LPC5410x Serial Wire Debug (SWD) 29.1 How to read this chapter ....405 29.6.4.4...
Page 463 UM10850 NXP Semiconductors Chapter 33: Supplementary information 31.5.8 Go ....... . 426 31.6.1...