Section 1 Overview; Overview - Hitachi H8/3006 Hardware Manual

1.1

Overview

The H8/3006 and H8/3007 are a series of microcontrollers (MCUs) that integrate system
supporting functions together with an H8/300H CPU core having an original Hitachi architecture.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,
enabling easy porting of software from the H8/300 Series.
The on-chip system supporting functions include RAM, a 16-bit timer, an 8-bit timer, a
programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication
interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller
(DMAC), and other facilities.
Four MCU operating modes offer a choice of bus width and address space size.
Table 1-1 summarizes the features of the H8/3006 and H8/3007.
Table 1-1 Features
Feature Description
CPU Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
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High-speed operation
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•
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16-Mbyte address space
Instruction features
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•
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Section 1 Overview

Sixteen 16-bit general registers
(also usable as sixteen 8-bit registers plus eight 16-bit registers, or as eight
32-bit registers)
Maximum clock rate: 20 MHz
Add/subtract: 100 ns
Multiply/divide: 700 ns
8/16/32-bit data transfer, arithmetic, and logic instructions
Signed and unsigned multiply instructions (8 bits x 8 bits, 16 bits x 16 bits)
Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
Bit accumulator function
Bit manipulation instructions with register-indirect specification of bit positions
1