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• Transmitting and Receiving Data Simultaneously (Synchronous Mode): Figure 12.20 shows a
sample flowchart for transmitting and receiving serial data simultaneously and indicates the
procedure to follow.
Initialize
Start of transmitting and receiving
Read TDRE flag in SSR
No
TDRE= 1
Write transmit data in TDR and
clear TDRE flag to 0 in SSR
Read ORER flag in SSR
ORER= 1
Read RDRF flag in SSR
No
RDRF= 1
Read receive data from RDR, and
clear RDRF flag to 0 in SSR
No
End of transmitting
and receiving?
Clear TE and RE bits to 0 in SCR
<End>
Note: When switching from transmitting or receiving to simultaneous transmitting and receiving,
clear both the TE bit and the RE bit to 0, then set both bits to 1 simultaneously.
Figure 12.20 Sample Flowchart for Simultaneous Serial Transmitting and Receiving
414
(1)
(2)
Yes
Yes
(3)
No
Error handling
(4)
Yes
(5)
Yes
(1)
SCI initialization: the transmit data output function of
the TxD pin and the read data input function of the
TxD pin are selected, enabling simultaneous
transmitting and receiving.
(2)
SCI status check and transmit data write: read SSR,
check that the TDRE flag is 1, then write transmit
data in TDR and clear the TDRE flag to 0.
Notification that the TDRE flag has changed from 0
to 1 can also be given by the TXI interrupt.
(3)
Receive error handling: if a receive error occurs,
read the ORER flag in SSR, then after executing the
necessary error handling, clear the ORER flag to 0.
Neither transmitting nor receiving can resume while
the ORER flag remains set to 1.
(4)
SCI status check and receive data read: read SSR,
check that the RDRF flag is 1, then read receive
data from RDR and clear the RDRF flag to 0.
Notification that the RDRF flag has changed from 0
to 1 can also be given by the RXI interrupt.
(5)
To continue transmitting and receiving serial data:
check the RDRF flag, read RDR, and clear the
RDRF flag to 0 before the MSB (bit 7) of the current
frame is received. Also check that the TDRE flag is
set to 1, indicating that data can be written, write
data in TDR, then clear the TDRE flag to 0 before
the MSB (bit 7) of the current frame is transmitted.
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