Emergency Status Register - Agilent Technologies 4155C Command Reference Manual

Figure 3-8
Table 3-5
Status Reporting Structure

Emergency Status Register

Emergency Status Register
This register consists of EVENT and event enable (MASK) registers.
You enable the desired bits of the EVENT register by using the MASK register. 1
enables, 0 masks the corresponding bit of EVENT register. The MASK register is
set by the :STATus:EMERgency:ENABle command. See "STATus Subsystem" in
Chapter 5 for details about this command.
Emergency Status Register
This register is not a standard SCPI register.
EMERgency Status Register
Bit Definition
0 Shut down
1 Interlock open
2 to 15 NOT USED
3-14 Agilent 4155C/4156C SCPI Command Reference, Edition 1
Explanation
This bit is set when SMU output is shut down
by the instrument to prevent damage to SMU.
This bit is set when the fixture lid is opened.
These bits are always zero.