Table 3.5-2 Reset Source And Oscillation Stabilization Delay Time - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 3 CPU
Upon completion of reset operation, the CPU restarts normal operation in main clock mode,
regardless of the operation mode (clock or standby mode) prior to the occurrence of the reset or
the reset source. If a reset occurs when main clock oscillation stops or during the main clock
oscillation stabilization delay time, therefore, the CPU enters the reset state in which it waits
until oscillation of the main clock becomes stable. Note, however, that if the power-on reset
option has not been selected, the main clock oscillation stabilization delay time is not taken
upon power-on operation or external reset.
The software or watchdog reset does not require the oscillation stabilization delay time during
operation in main clock mode. During operation in subclock mode, however, the reset requires
the oscillation stabilization delay time because main clock oscillation is off in subclock mode.
Table 3.5-2 summarizes the relationships among each reset source, main clock oscillation
stabilization delay time, and reset operation (mode fetch).

Table 3.5-2 Reset Source and Oscillation Stabilization Delay Time

Reset
source
External
reset (*1)
Software or
watchdog
reset
Power-on reset
*1:
*2:
*3:
54
Operation
state
Power-on
sequence,
stop mode,
or subclock
mode
Main clock
mode
Subclock
mode
The external reset during operation in main clock mode does not require the oscillation
stabilization delay time. The CPU performs reset operation after waking up from the
external reset.
When the reset output enable option has been selected, the "L" level signal is output
to the RST pin for the main clock oscillation stabilization delay time.
When the reset output enable option has been selected, the "L" level signal is output
to the RST pin for four instruction cycles.
Reset operation and main clock oscillation stabilization
delay time
Product with power-on
reset function
Performs reset operation
after the oscillation
stabilization delay time has
passed and the CPU wakes
up from the external reset.
(*2)
Performs reset operation after generating a reset for 4
instruction cycles. (*3)
Performs reset operation after the main clock oscillation
stabilization delay time has passed. (*2)
Performs reset operation
after the main clock
oscillation stabilization delay
time has passed after turning
the power on. (*2)
Product without power-on
reset function
Remains in the reset state
until the CPU wakes up from
the external reset. When the
CPU wakes up from the
reset, it performs reset
operation.
Requires the external reset
circuit for generating a reset
continuously until oscillation
of the main clock becomes
stable after turning the power
on.