3.2 Reset Factors and Oscillation Stabilization Wait Time
The MB90420 (A)/425 (A) series has 6 reset factors. The oscillation stabilization wait time at a reset
depends on the reset factors.
n Reset sources and oscillation stabilization wait time
Table 3-2 and Figure 3-1 show the oscillation stabilization wait times at power-on reset.
Vcc
CLK
CPU Operation
HCLK: Oscillation clock
Fig. 3.1 Oscillation Stabilization Wait Time of Evaluation Products/Flash and
Table 3-2 shows the reset factors and oscillation stabilization wait time.
Table 3-2 Reset Factors and Oscillation Stabilization Wait Times
Reset
Power-on
Power rise
Watchdog
Overflow of watchdog timer
External
Input "L" level to RSTX pin
Low-voltage
Detection of low power supply
detection*
voltage
CPU Operation
Overflow of CPU operation
detection*
detection timer
Writing 0 to RST bit of low power
Software
consumption mode control register
(LPMCR)
*
: This factor causes a reset only for the MB90420A and MB90425A series.
HCLK
: Oscillation clock frequency original oscillation
WS1, WS0 : Clock selection register CKSCR oscillation stabilization wait time selection bit
Figure 3.2 shows the oscillation stabilization wait time at power-on reset.
RESET
17
17
2
/HCLK
2
/HCLK
Voltage-lowering
Oscillation
circuit stabilization
stabilization
wait time
wait time
Mask Products at Power-on Reset
Reset Factor
The Oscillation Stabilization Wait Time
The one indicated in parentheses is obtained when the
oscillation clock frequency is 4 MHz.
18
2
/HCLK (about 65.536 ms)
Not taken: However, the WS1 and WS0 bits are initialized to
11.
Not taken: However, the WS1 and WS0 bits are initialized to
11.
18
2
/HCLK (about 65.536 ms)
Not taken: However, the WS1 and WS0 bits are initialized to
11.
Not taken: However, the WS1 and WS0 bits are initialized to
11.
3-5