Operation Of The External Interrupt And Nmi Controller - Fujitsu FR60 Hardware Manual

9.3

Operation of the External Interrupt and NMI Controller

After a request level and an enable register are specified, if a request specified in the
external interrupt request level setting register (ELVR) is input to the corresponding
pin, this module generates an interrupt request signal to the interrupt controller.
■ Operation of an External Interrupt
For simultaneous interrupt requests, the interrupt controller determines the interrupt request with
the highest priority and generates an interrupt for it.
Figure 9.3-1 shows external interrupt operation.
External interrupt
ELVR
EIRR
ENIR
Source
■ Return from Standby
To use an external interrupt to return from the stop state, use an "H" level request as the input
request regardless of setting the external interrupt request level setting register (ELVR).
Note:
Cut off the pull-up for the INT0 to INT7 pin in the stop state.
■ Operating Procedure for an External Interrupt
Set up a register located inside the external interrupt block as follows:
1) Set the general-purpose I/O port served dual use as the pin for the external interrupt input to
input port.
2) Disable the target bit in the enable register.
3) Set the target bit in the request level setting register.
4) Clear the target bit in the interrupt register.
5) Enable the target bit in the enable register.
Simultaneous writing of 16-bit data is supported for steps 4) and 5).
Before setting a register in this module, you must disable the enable register. In addition, before
enabling the enable register, you must clear the interrupt Request Register. This procedure is
required to prevent an interrupt source from occurring by mistake while a register is being set or
an interrupt is enabled.
CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER
Figure 9.3-1 External Interrupt Operation
Resource
Interrupt controller
request
ICR y y
ICR x x
IL
CMP
ILM
CPU
CMP
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