Operation Of External Interrupt/Nmi Controller - Fujitsu MB91260B Series Hardware Manual

CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER
6.3

Operation of External Interrupt/NMI Controller

If, after a request level and an enable register are defined, a request defined in the ELVR
register is input to the corresponding pin, this module generates an interrupt request
signal to the interrupt controller. For simultaneous interrupt requests from resources,
the interrupt controller determines the interrupt request with the highest priority and
generates an interrupt for it.
■ Operation of an External Interrupt
Figure 6.3-1 shows the external interrupt operation.
External Interrupt
Source
■ Return from Standby
To use an external interrupt to return from the standby state in the clock stop mode, set "H" level or "L"
level request as the input request.
If you use an edge request, the device does not return from the stop state in clock stop mode.
Please make sure to disable unused channels before entering a standby mode.
■ Operating Procedure for an External Interrupt
Set up a register located inside the external interrupt controller as follows:
1. Set the general-purpose I/O port served dual use as external interrupt input pin as the input port.
2. Disable the target bit in the enable register.
3. Set the target bit in the request level setting register.
4. Clear the target bit in the interrupt source register.
5. Enable the target bit in the enable register.
(Simultaneous writing of 16-bit data is supported for steps 4. and 5.)
Before setting a register in this module, you must disable the enable register. In addition, before enabling
the enable register, you must clear the interrupt source register. This procedure is required to prevent an
interrupt source from occurring by mistake while a register is being set or an interrupt is enabled.
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Figure 6.3-1 External Interrupt Operation
Resource request
ELVR
EIRR
ENIR
Interrupt controller
ICR vv
CMP
ICR xx
CPU
IL
CMP
ILM