Transfer Source Address Setting Register (Dmasa0-4); Transfer Destination Address Setting Register (Dmada0-4); Table 2-3: Dmacbn-Ii - Fujitsu FR Series Application Note

Bit
Name Explanation
No.
18 DSS2 End Code-1
17 DSS1
... ... End Code-2
DSS0
16
15 SASZ7 Source
... ... Address Count
8 SASZ0 Size
7 Destination
DASZ7
... ... Address Count
0 DASZ0 Size

2.3.3 Transfer Source Address Setting Register (DMASA0-4)

These registers select transfer source address.

2.3.4 Transfer Destination Address Setting Register (DMADA0-4)

These registers select transfer destination address.
Transfer source and destination address setting registers can't be read when the transfer is
going on. If one tries to read them while the ongoing transfer, the address before the transfer
is read and if read after the transfer then the next access address is read.
MCU-AN-300059-E-V11
DIRECT MEMORY ACCESS
Chapter 2 Direct Memory Access
Initial
Value
Value
0
0
1
0,0
0,1
0,0
1,0
1,1
x -
x -

Table 2-3: DMACBn-II

- 12 -
Operation
Initial Value
DMA stopped temporarily due to
DMAH bit or PAUS bit or an interrupt)
Initial Value
Address error (underflow/overflow) –
ERIE
Transfer stop request – ERIE
Transfer ended normally – EDIE
Specifies the increment or decrement
width for the transfer source address
(DMASA) of the corresponding channel
in each transfer operation.
Specifies the increment or decrement
width for the transfer destination
address (DMADA) of the
corresponding channel in each
transfer operation.
© Fujitsu Microelectronics Europe GmbH