Event Count Mode - Fujitsu F2MC-16LX Hardware Manual

16.3.4

Event Count Mode

When the input edge from the TIN pin is counted, the 16-bit counter is counted down
and the counter underflow occurs, the CPU interrupt request is generated. In addition,
the toggle waveform or the rectangular waveform can be output from the TOT pin.
Event Count Mode
When the count operation is permitted (CNTE = 1 for TMCSR) and the counter is started (TRG = 1 for
TMCSR), the 16-bit reload register (TMRLR) value is loaded to the counter. Every time when the valid
edge (rising edge, falling edge, or both edge can be selected) of pulses (external count clock) input to the
TIN pin is detected, the count down is performed. When the count permission bit and the software trigger
bit are simultaneously set to "1", the count is started at the same time of the count permission.
Operation of Reload mode
When the counter value underflows ("0000
loaded to the counter and the count operation is continued. At this moment, if the underflow interrupt
request flag bit (UF) is set to "1" and the interrupt request permission bit (INTE of TMCSR) is "1", the
interrupt request is generated. In addition, the toggle waveform which reverses at every underflow can be
output from the TOT pin.
Figure 16.3-10 shows Count operation (event count mode) at reload mode.
Figure 16.3-10 Count Operation (Event Count Mode) at Reload Mode
Count clock
Counter
Data load
signal
UF bit
CNTE bit
TRG bit
T*
TOT pin
T: Machine cycle
*: It takes 1T time from trigger input to loading of reload data.
Note:
Use the 4/φ or more "H" width and "L" width of the clock to be input to the TIN pin.
−1
Reload 0000 Reload
H
data data
CHAPTER 16 16-BIT RELOAD TIMER
" → "FFFF
"), the 16-bit reload register (TMRLR) value is
H H
−1 −1
0000 Reload
H
data
−1
0000 Reload
H
data
401