Event Count Mode - Fujitsu F2MC-16LX Hardware Manual

16.3.4 Event Count Mode

In this mode, the counter counts input edges from the TIN pin to count down the 16-bit
counter and generate an interrupt request to the CPU when a counter underflow
occurs. The TOT pin can output either a toggle waveform or a square wave.
I Event Count mode
When count operation is allowed (TMCSR: CNTE=1) to start the counter (TMCSR: TRG=1),
data from the 16-bit reload registers (TMRLR) is loaded into the counter for a countdown
whenever a valid edge (leading or trailing can be selected) of pulses (external count clock) input
to the TIN pin is detected. When both the count enable bit and software trigger bit are set to "1",
counting will start as soon as counting becomes enabled.
Operation in reload mode
If the counter value has an underflow (0000
(TMRLR) is loaded into the counter to continue counting. In this case, an interrupt request is
issued when the underflow flag bit for interrupt requests (UF) and enable bit for interrupt
requests (TMCSR: INTE) are both set to "1". The TOT pin outputs a toggle waveform, which is
reversed at every occurrence of underflow. Figure 16.3-10 "Count operation in reload mode
(event count mode)" shows the counting operation in reload mode.
Figure 16.3-10 Count operation in reload mode (event count mode)
TIN pin
Counter
Data load signal
UF bit
CNTE bit
TRG bit
TOT pin
T: Machine cycle
*1: It takes 1T from trigger input to loading reload data.
Note:
Both the "H" width and "L" width of clock input to the TIN pin shall be 4/φ or more.
Reload
Reload
-1 0000
H
data
data
*1
T
CHAPTER 16 16-BIT RELOAD TIMER
--> FFFF ), data from the 16-bit reload registers
H H
Reload
-1 0000 -1
H
data
Reload
0000 -1
H
data
327