Table of Contents
Advertisement
CHAPTER 10 WATCHDOG TIMER
10.1 Overview of Watchdog Timer
10.1
Overview of Watchdog Timer
The watchdog timer is a 2-bit counter operating with an output of the time-base timer or
clock timer as the count clock and resets the CPU when the counter is not cleared for a
preset period of time.
■ Functions of Watchdog Timer
The watchdog timer is a counter for preventing programs from hanging up. The timer must be cleared at
specified intervals after being activated. If the watchdog timer is not cleared within a certain time due to an
infinite loop of the program, etc., a watchdog reset is generated to the CPU. The interval time of the
watchdog timer can be set by the watchdog timer control register (WDTC), as shown in Table 10.1-1.
When the watchdog timer is not cleared, a watchdog reset occurs following the time between the minimum
time interval and the maximum time interval. The counter must be cleared within the time of the minimum
time interval.
Table 10.1-1 Interval Time of Watchdog Timer
WT1
WT0
0
0
0
1
1
0
1
1
*: Value for when operating at oscillator clock (HCLK) of 6 MHz. The maximum and minimum watchdog timer interval
time and the number of oscillation clock cycles are determined by the timing of clear operation. The interval time will be
3.5 to 4.5 times of the count clock (supplied clock of time-base timer) cycle. For the watchdog timer interval time, see
"10.4 Operations of Watchdog Timer".
Note:
The watchdog counter is a 2-bit counter that counts carry-up signals from the time-base timer.
Therefore, when the time-base timer is cleared, the time period until the occurrence of a watchdog
timer reset may be longer than the preset period of time.
Reference:
When the watchdog timer is activated, it is initialized and set to the stopped state by a reset upon
power-on or by a reset by the watchdog. Also, the watchdog counter is cleared by writing to the reset
by the external pin, the software reset, and the watchdog control bit (WTE) of the watchdog timer
control register and by changing to sleep and stop mode, but the watchdog timer is still activated.
184
Interval Time
*
Min.
Approx. 2.39 ms
Approx. 9.56 ms
Approx. 38.23 ms
Approx. 305.83 ms
FUJITSU MICROELECTRONICS LIMITED
*
Max.
Approx. 3.07 ms
Approx. 12.29 ms
Approx. 49.15 ms
Approx. 393.22 ms
MB90335 Series
Clock cycle
14
± 2
11
(2
)/HCLK
16
± 2
13
(2
)/HCLK
18
± 2
15
(2
)/HCLK
21
± 2
18
(2
)/HCLK
CM44-10137-6E
Advertisement
Table of Contents
