Overview Of Watchdog Timer; Table 6.1-1 Watchdog Timer Interval Time - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 6 WATCHDOG TIMER
6.1

Overview of Watchdog Timer

The watchdog timer is a 1-bit counter that uses either output from the timebase timer
operating with the main clock or from the watch prescaler operating with the subclock.
The watchdog timer resets the CPU if not cleared within a fixed time after activation.
Watchdog Timer Function
The watchdog timer is a counter provided to guard against program runaway. Once activated,
the counter must be repeatedly cleared within a fixed time interval. If the program becomes
trapped in an endless loop or similar and does not clear the counter within the fixed time, the
watchdog timer generates a four-instruction cycle watchdog reset to the CPU.
Either a timebase timer output or a watch prescaler output can be selected for the count clock of
the watchdog timer.
Table 6.1-1 lists the watchdog timer interval times. If not cleared, the watchdog timer generates
a watchdog reset at a time between the minimum and maximum times listed. Clear the counter
within the minimum time given in the table.

Table 6.1-1 Watchdog Timer Interval Time

Minimum time
Maximum time
*1: Divide-by-two main clock source oscillation (F
*2: Subclock oscillation (F
Reference:
See Section 6.4, "Operation of Watchdog Timer" for the details on the minimum and
maximum time of the watchdog timer interval times.
Check:
The watchdog timer counter is cleared whenever the timebase timer is cleared (TBTC: TBR
= "0") with the timebase timer output selected as the count clock. The counter is also
cleared whenever the watch prescaler is cleared (WPCR: WCLR = "0") with the watch
prescaler selected as the count clock. If the counter (timebase timer or watch prescaler)
used as the count clock is cleared repeatedly in the watchdog timer interval time, therefore,
the counter stops serving as the watchdog timer.
Tip:
The watchdog timer counter is cleared whenever the device changes to sleep mode, stop
mode, or watch mode. Operation halts until the device returns to normal operation (RUN
state).
146
Timebase timer output
(at main clock oscillation of 4.2 MHz)
Approx. 998.6 ms
Approx. 1997.2 ms
) frequency × watch prescaler count (2
CL
Count clock
(at subclock oscillation of 32.768 kHz)
*1
) × timebase timer count value (2
CH
Watch prescaler output
*2
500 ms
1000 ms
14
)
21
)