I/O Port Registers - Fujitsu FR60 Hardware Manual

32-bit microcontroller mb91301 series

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CHAPTER 5 I/O PORT

I/O Port Registers

This section describes the configuration and functions of the I/O port registers.

■ Configuration of the Port Data Registers (PDR)

Shown below is the configuration of the port data registers (PDR).

Figure 5.2-1 Configuration of the Port Data Registers (PDR)

Address: 000000

Address: 000001

Address: 000002

Address: 000006

Address: 000008

Address: 000009

Address: 00000A

Address: 00000B

Address: 000010

Address: 000011

Address: 000013

PDR0 to PDR2, PDR6, PDR8 to PDRB, PDRG, PDRH and PDRJ are the input/output data

registers for the I/O port.

Input/output is controlled by the corresponding DDR0 to DDR2, DDR6, DDR8 to DDRB, DDRG,

DDRH and DDRJ, and PFR6, PFR8, PFR9, PFRA1, PFRB1, PFRB2, PFRA2, PFRG, PFRH

There are not any PFR (Port Function Register) for P00 to P07, P10 to P17, P20 to P27.

Initial value

Initial value

Initial value

Initial value

Initial value

Initial value

Initial value

Initial value

Initial value

Initial value

Initial value