Operation; Transfer Mode; Step Transfer; Block Transfer - Fujitsu FR Series Application Note

2.4 Operation

The DMAC has 5 channels and all these 5 channel functions can be set independently of
each other.

2.4.1 Transfer Mode

Each DMAC channel performs transfer according to the transfer mode set by the MOD[1:0]
bits of its DMACB register.

2.4.1.1 Step Transfer

Step transfer is performed when the block size (BLK[3:0] of DMACA) is specified as 1 in the
block transfer mode (MOD[1:0] = 0 of DMABA).
1. In case of step transfer after the transfer request is received, one transfer operation
(of single byte/half-word/word as specified by WS[1:0] bits of DMABA) is performed.
2. The peripheral interrupt, if any, which had initiated the transfer request gets cleared
by DMAC
3. Then the transfer is stopped with DSS[1:0] of DMABA register gets set to B'11
indicating transfer ended normally.
4. After the transfer end the DMASA, DMADA registers and BLK[1:0] and DTC[15:00]
bits of DMACA register gets updated accordingly.
If there is one more transfer request during the transfer is happening then it would be
ignored.

2.4.1.2 Block Transfer

Block transfer is performed when the block size (BLK[3:0] of DMACA) is specified as any
value greater than 1 in the block transfer mode (MOD[1:0] = B'00 of DMABA).
1. In case of block transfer after the transfer request is received, a single block transfer
unit is transferred and then the transfer is stopped. If WS[1:0] of DMABA is B'10 and
BLK[3:0] of DMACA is B'1010, then the single block transfer unit would be 10 (32-
bit) words.
2. After this the DMASA, DMADA registers gets updated accordingly.
3. The BLK[1:0] of DMACA register become 0 and DTC[15:0] bits of DMACA register
gets decremented by 1.
4. The peripheral interrupt, if any, which had initiated the transfer request, gets cleared
by DMAC.
5. Then the DMAC waits for next transfer request. During this time the CPU can get
access of the buses until the DMAC gets next transfer request.
6. Upon getting the next such transfer requests steps 1 to 4 are performed unless and
until the DTC[15:0] becomes 0.
7. Once the DTC[15:0] becomes 0, the transfer is stopped with DSS[1:0] of DMABA
register gets set to B'11 indicating transfer ended normally.
8. If the reload is enabled then the DMAC waits for next transfer request.
MCU-AN-300059-E-V11
DIRECT MEMORY ACCESS
Chapter 2 Direct Memory Access
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