Ei Os Operation - Fujitsu MB90420/5 (A) Series Hardware Manual

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6.6.3 EI OS Operation
The CPU transfers data when the interrupt request is issued from the resource and starting of EI
already set in the corresponding interrupt control register (ICR). After termination of data transfer for the
specified count, the hardware interrupt handling is performed automatically.
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n EI
OS operation procedure
Figure 6.18 shows the operation flow of the EI
Termination request from
Memory indicated by BAP
2
ISD : EI OS descriptor
2
ISCS : EI OS status register
IF : IOA updating/fixing selection bit of EI
BW : Transfer data length specification bit of EI
BF : BAP updating/fixing selection bit of EI
DIR : Data transfer direction specification bit of EI
Interrupt request issued
from resource
NO
ISE = 1
YES
Read ISD/ISCS
YES
resource
NO
YES
DIR = 1
NO
Data indicated by IOA
(Data transfer)
YES
IF = 0
Updating value
NO
depends on BW
YES
BF = 0
NO
Updating value
depends on BW.
Decrement DCT (−1)
YES
DCT = 00
NO
Set S1 and S0 to 00
Clear resource interrupt
request
Return to CPU
operation
2
OS status register (ISCS)
2
OS status register (ISCS)
2
OS status register (ISCS)
2
OS status register (ISCS)
Fig. 6.18 Operation Flow of EI
INTERRUPT
2
OS by the microcode in the CPU.
Interrupt sequence
NO
SE = 1
Data indicated by BAP
(Data transfer)
Memory indicated by BAP
Update IOA
Update BAP
2
EI OS termination processing
Set S1 and S0 to 01.
Clear ISE to 0.
Interrupt sequence
2
SE : EI OS termination control bit of EI
DCT : Data counter
IOA : I/O register address pointer
BAP : Buffer address pointer
2
ISE : EI OS enable bit of interrupt control register (ICR)
2
S1, S0 : EI OS status of interrupt control register (ICR)
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YES
Set S1 and S0 to 11.
2
OS status register (ISCS)
OS
2
OS is