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CHAPTER 3 INTERRUPT
3.4 Hardware Interrupt
3.4.4
Multiple Interrupts
Multiple hardware interrupts can be implemented. To do so, set different interrupt levels
for interrupt level set bits (IL0 to IL2) of the ICR in response to two or more interrupt
requests from a peripheral function. However, multiple EI
cannot be started.
■ Multiple Interrupts
If an interrupt request with a higher interrupt level is generated during execution of the interrupt handling
routine, this higher interrupt level request is accepted with the current interrupt handling suspended. After
completion of the higher interrupt level, control returns to the handling of the suspended interrupt. The
interrupt level can be set to "0" to "7". If it is set to "7", the CPU will accept no interrupt request.
If a new interrupt at the same or a lower level is generated during execution of the current interrupt
handling, the new one remains pending until the current one is completed, unless the I flag changes the
ILM. Activation of the multiple interrupt function during the interrupt is temporarily disabled by setting the
I flag in the condition code register (CCR) to "disable" (CCR:I = 0), or setting the interrupt level mask
register (ILM) to "disable" (ILM = 000
Note:
However, multiple EI
service (EI
and μDMAC requests remain pending.
66
2
OS and multiple μDMAC cannot be started. If an extended intelligent I/O
2
OS) or μDMAC process is in progress, all the other interrupt requests and all the EI
FUJITSU MICROELECTRONICS LIMITED
2
OS and multiple μDMAC
) in the interrupt handling routine.
B
MB90335 Series
2
CM44-10137-6E
OS
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