Multiple Interrupts; Figure 3.4-3 Example Of Multiple Interrupts - Fujitsu F2MC-8L Series Hardware Manual

3.4.3

Multiple Interrupts

Multiple interrupts can be performed by setting different interrupt levels to the
interrupt level setting register (ILR1 to ILR3) for two or more interrupt requests from
peripheral functions.
Multiple Interrupts
If the interrupt request having the higher interrupt levels occurs during the interrupt processing
routines, the CPU halts the current interrupt process and switches to accept the interrupt with
the higher priority. Interrupt levels can be set in the range 1 to 3. However, the CPU does not
accept interrupt requests set to interrupt level 3.
Example of Multiple Interrupts
As an example of multiple interrupt processing, assume that an external interrupt has a higher
priority than the timer interrupt. The timer interrupt is set to level 2 and the external interrupt is
set to level 1. Figure 3.4-3 shows the processing when the external interrupt occurs during
execution of timer interrupt processing.
Initialize peripheral
Timer interrupt occurs
Restart main program
• During execution of timer interrupt processing, the interrupt level bits in the condition code
register (CCR: IL1, IL0) are automatically set to the same value as the interrupt level setting
register (ILR1, ILR2, ILR3) corresponding to the timer interrupt (level 2 in this example). If
the interrupt request set to higher interrupt level (level 1 in this example) occurs at this time,
the interrupt processing has priority.
• To temporarily disable multiple interrupts during the timer interrupt, the interrupt enable flag
in the condition code register is set to "interrupts disabled" (CCR: I = "0") or the interrupt
level bits (IL1, IL0) set to "00".
• On execution of the interrupt return instruction (RETI) at the completion of interrupt
processing, the CPU restores the program counter (PC) and program status (PS) values

Figure 3.4-3 Example of Multiple Interrupts

Main program Timer interrupt processing
Interrupt level 2
(CCR:IL1, IL0 = "10")
(1)
(2)
Restart
(8)
External interrupt processing
Interrupt level 1
(CCR:IL1, IL0 = "01")
(3)
External interrupt
occurs
Halt
Timer interrupt
(6)
processing
(7)
Recover from timer interrupt
3.4 Interrupts
(4) External interrupt
processing
(5)
External interrupt
returns
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