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Operating Modes
11
RS27
23
The ESAI RSMA and RSMB registers are located at x:$FFFFBB and x:$FFFFBC respectively. The ESAI_1 RSMA and RSMB registers are
located at y:$FFFF9B and y:$FFFF9C respectively.
When bit number N in the RSM register is cleared, the data from the enabled receivers input pins are shifted into their receive shift registers
during slot number N. The data is not transferred from the receive shift registers to the receive data registers, and neither the RDF nor the ROE
flag is set. This means that during a disabled slot, no receiver full interrupt is generated. The DSP is interrupted only for enabled slots.
When bit number N in the RSM is set, the receive sequence is as usual: data which is shifted into the enabled receivers shift registers is
transferred to the receive data registers and the RDF flag is set.
Data written to the RSM affects the next received frame. The frame being received is not affected by this data and would comply to the last
RSM setting. Data read from RSM returns the last written data.
After hardware or software reset, the RSM register is preset to $FFFFFFFF, which means that all 32 possible slots are enabled for data
reception.
When operating in normal mode, bit 0 of the mask register must be set to one, otherwise no input is
received.
8.4
Operating Modes
ESAI operating mode are selected by the ESAI control registers (TCCR, TCR, RCCR, RCR and SAICR). The main operating mode are
described in the following paragraphs.
8.4.1
ESAI After Reset
Hardware or software reset clears the port control register bits and the port direction control register bits, which configure all ESAI I/O pins
as disconnected. The ESAI is in the individual reset state while all ESAI pins are programmed as GPIO or disconnected, and it is active only
if at least one of the ESAI I/O pins is programmed as an ESAI pin.
8.4.2
ESAI Initialization
The correct way to initialize the ESAI is as follows:
1.
Hardware, software, ESAI individual, or STOP reset.
2.
Program ESAI control and time slot registers.
3.
Write data to all the enabled transmitters.
4.
Configure at least one pin as ESAI pin.
During program execution, all ESAI pins may be defined as GPIO or disconnected, causing the ESAI to stop serial activity and enter the
individual reset state. All status bits of the interface are set to their reset state; however, the control bits are not affected. This procedure allows
the DSP programmer to reset the ESAI separately from the other internal peripherals. During individual reset, internal DMA accesses to the
data registers of the ESAI are not valid and data read is undefined.
The DSP programmer must use an individual ESAI reset when changing the ESAI control registers (except for TEIE, REIE, TLIE, RLIE,
TIE, RIE, TE0-TE5, RE0-RE3) to ensure proper operation of the interface.
8-32
10
9
8
7
RS26
RS25
RS24
RS23
22
21
20
19
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 8-18. RSMB Register
NOTE
DSP56374 Users Guide, Rev. 1.2
6
5
4
3
RS22
RS21
RS20
RS19
18
17
16
15
RS31
2
1
0
RS18
RS17
RS16
14
13
12
RS30
RS29
RS28
Freescale Semiconductor
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