ST STM32L4+ Series Reference Manual page 1896

Serial audio interface (SAI)
53.4 SAI functional description
53.4.1 SAI block diagram
Figure 546
external signals.
SAI
SAI_ACR1
sai_a_
Clock generator
ker_ck
Audio block A
sai_pclk
sai_b_
Clock generator
ker_ck
Audio block B
SAI_BCR1
1. These signals might not be available for all SAI instances. Refer to
The SAI is mainly composed of two audio subblocks with their own clock generator. Each
audio block integrates a 32-bit shift register controlled by their own functional state machine.
Data are stored or read from the dedicated FIFO. FIFO may be accessed by the CPU, or by
DMA in order to leave the CPU free during the communication. Each audio block is
independent. They can be synchronous with each other.
An I/O line controller manages a set of 4 dedicated pins (SD, SCK, FS, MCLK) for a given
audio block in the SAI. Some of these pins can be shared if the two subblocks are declared
as synchronous to leave some free to be used as general purpose I/Os. The MCLK pin can
be output, or not, depending on the application, the decoder requirement and whether the
audio block is configured as the master.
If one SAI is configured to operate synchronously with another one, even more I/Os can be
freed (except for pins SD_x).
1896/2301
shows the SAI block diagram while
Figure 546. SAI functional block diagram
32-bit APB bus
sai_a_gbl_it sai_a_dma
APB Interface
FIFO
Configuration
and status
registers
FIFO
Configuration
and status
registers
APB Interface
sai_b_gbl_it sai_b_dma
32-bit APB bus
RM0432 Rev 6
Table 370 and
Audio block A
FIFO ctrl
FSM
32-bit shift register
Audio block B
FIFO ctrl
FSM
32-bit shift register
Section 53.3: SAI implementation
Table 371 list SAI internal and
SAI_GCR
Synchro
sai_sync_out_sck
ctrl out
sai_sync_out_fs
FS_A
SCK_A
SD_A
MCLK_A
FS_B
SCK_B
SD_B
MCLK_B
(1)
D[4:1]
PDM_IF
(1)
CK[4:1]
sai_sync_in_sck
sai_sync_in_fs
for details.
RM0432
MSv62453V1