ST STM32L4+ Series Reference Manual page 1890

Serial peripheral interface (SPI)
Bit 7 BSY: Busy flag
Note: The BSY flag must be used with caution: refer to
Bit 6 OVR: Overrun flag
Bit 5 MODF: Mode fault
Bit 4 CRCERR: CRC error flag
Note: This flag is set by hardware and cleared by software writing 0.
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TXE: Transmit buffer empty
Bit 0 RXNE: Receive buffer not empty
52.6.4 SPI data register (SPIx_DR)
Address offset: 0x0C
Reset value: 0x0000
15 14 13
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Bits 15:0 DR[15:0]: Data register
Note: Data is always right-aligned. Unused bits are ignored when writing to the register, and
1890/2301
0: SPI not busy
1: SPI is busy in communication or Tx buffer is not empty
This flag is set and cleared by hardware.
Procedure for disabling the SPI on page
0: No overrun occurred
1: Overrun occurred
This flag is set by hardware and reset by a software sequence.
0: No mode fault occurred
1: Mode fault occurred
This flag is set by hardware and reset by a software sequence. Refer to
(MODF) on page 1880 for the software sequence.
0: CRC value received matches the SPIx_RXCRCR value
1: CRC value received does not match the SPIx_RXCRCR value
0: Tx buffer not empty
1: Tx buffer empty
0: Rx buffer empty
1: Rx buffer not empty
12 11 10 9
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Data received or to be transmitted
The data register serves as an interface between the Rx and Tx FIFOs. When the data
register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See
Section 52.4.9: Data transmission and reception
read as zero when the register is read. The Rx threshold setting must always
correspond with the read access currently used.
1871.
8 7 6
DR[15:0]
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procedures).
RM0432 Rev 6
Section 52.4.10: SPI status flags
Section : Mode fault
5 4 3 2
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RM0432
and
1 0
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