Lptim Interrupt Clear Register (Lptim_Icr) - ST STM32F410 Reference Manual

RM0401
18.7.2

LPTIM interrupt clear register (LPTIM_ICR)

Address offset: 0x004
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 Reserved, must be kept at reset value.
Bit 20 Reserved, must be kept at reset value.
Bit 19 Reserved, must be kept at reset value.
Bits 18:16 Reserved, must be kept at reset value.
Bit 15 Reserved, must be kept at reset value.
Bit 14 Reserved, must be kept at reset value.
Bit 13 Reserved, must be kept at reset value.
Bit 12 Reserved, must be kept at reset value.
Bit 11 Reserved, must be kept at reset value.
Bit 10 Reserved, must be kept at reset value.
Bit 9 Reserved, must be kept at reset value.
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 DOWNCF: Direction change to down clear flag
Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register.
Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to
Section 18.3: LPTIM
Bit 5 UPCF: Direction change to UP clear flag
Writing 1 to this bit clear the UP flag in the LPTIM_ISR register.
Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to
Section 18.3: LPTIM
Bit 4 ARROKCF: Autoreload register update OK clear flag
Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register
Bit 3 CMPOKCF: Compare register update OK clear flag
Writing 1 to this bit clears the CMPOK flag in the LPTIM_ISR register
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
implementation.
implementation.
24 23 22
Res. Res. Res.
8 7 6
DOWN
Res. Res. UPCF
CF
w
RM0401 Rev 3
Low-power timer (LPTIM)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
ARRO CMPO EXTTR
KCF KCF IGCF
w w w w
17 16
Res. Res.
1 0
ARRM CMPM
CF CF
w w
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