Lptim Interrupt Clear Register (Lptim_Icr) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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Low-power timer (LPTIM)

Bit 3 CMPOK: Compare register update OK

CMPOK is set by hardware to inform application that the APB bus write operation to the

LPTIM_CMP register has been successfully completed.

Bit 2 EXTTRIG: External trigger edge event

EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger

input has occurred. If the trigger is ignored because the timer has already started, then this flag is

not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.

Bit 1 ARRM: Autoreload match

ARRM is set by hardware to inform application that LPTIM_CNT register's value reached the

LPTIM_ARR register's value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the

LPTIM_ICR register.

Bit 0 CMPM: Compare match

The CMPM bit is set by hardware to inform application that LPTIM_CNT register value reached the

LPTIM_CMP register's value.

LPTIM interrupt clear register (LPTIM_ICR)

Address offset: 0x004

Reset value: 0x0000 0000

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 REPOKCF: Repetition register update OK clear flag

Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register.

Bit 7 UECF: Update event clear flag

Writing 1 to this bit clear the UE flag in the LPTIM_ISR register.

Bit 6 DOWNCF: Direction change to down clear flag

Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register.

Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to

Section 28.3: LPTIM

Bit 5 UPCF: Direction change to UP clear flag

Writing 1 to this bit clear the UP flag in the LPTIM_ISR register.

Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to

Section 28.3: LPTIM

Bit 4 ARROKCF: Autoreload register update OK clear flag

Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register

Bit 3 CMPOKCF: Compare register update OK clear flag

Writing 1 to this bit clears the CMPOK flag in the LPTIM_ISR register

implementation.

RM0453 Rev 1

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Lptim Interrupt Clear Register (Lptim_Icr) - ST STM32WL5 Series Reference Manual

LPTIM interrupt clear register (LPTIM_ICR)

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