Design Considerations For Ports 3 And 4; Eport - Intel 8XC196NT User Manual

8XC196NT USER'S MANUAL
6.4.3

Design Considerations for Ports 3 and 4

When EA# is active, ports 3 and 4 will function only as the address/data bus. In these circum-
stances, an instruction that operates on P3_REG or P4_REG causes a bus cycle that reads from
or writes to the external memory location corresponding to the SFR's address. (For example, writ-
ing to P4_REG causes a bus cycle that writes to external memory location 1FFDH.) Because
P3_REG and P4_REG have no effect when EA# is active, the bus will float during long periods
of inactivity (such as during a BMOV or TIJMP instruction).
When EA# is inactive, ports 3 and 4 output the contents of the P3_REG and P4_REG registers.
Because these registers reset to FFH and the P34_DRV register resets to 00H (open-drain mode),
ports 3 and 4 will float unless you either connect external resistors to the pins, write zeros to the
P3_REG and P4_REG registers, or write ones to the P34_DRV register.
6.5

EPORT

The EPORT is a four-bit, bidirectional, memory-mapped I/O port. This port provides the address
signals necessary to support extended addressing. It must be accessed using indirect or indexed
addressing, and it cannot be windowed. If one or more extended address pins are unnecessary in
an application, the unused port pins can be used for I/O. Figure 6-4 shows a block diagram of the
EPORT.
Table 6-14 lists the EPORT pins with their extended-address signals. Table 6-15 lists the registers
that affect the function and indicate the status of EPORT pins.
EPORT.0
EPORT.1
EPORT.2
EPORT.3
Table 6-15. EPORT Control and Status Registers
Mnemonic Address
EP_DIR 1FE3H
6-18
Table 6-14. EPORT Pins
Extended-address
Port Pin
Signal
A16
A17
A18
A19
EPORT Direction
In I/O mode, each bit of EP_DIR controls the direction of the corre-
sponding pin. Clearing a bit configures a pin as a complementary
output; setting a bit configures a pin as either an input or an open-
drain output. (Open-drain outputs require external pull-ups).
Any pin that is configured for its extended-address function is forced
to the complementary output mode except during reset, hold, idle,
and powerdown.
Signal Type
I/O
I/O
I/O
I/O
Description