Main Features; Block Diagram; Wakeup Event Management; Figure 19. External Interrupt/Event Controller Block Diagram - ST STM32F101xx Reference Manual

Interrupts and events
9.2.1

Main features

The EXTI controller main features are the following:
●
Independent trigger and mask on each interrupt/event line
●
Dedicated status bit for each interrupt line
●
Generation of up to 20 software event/interrupt requests
●
Detection of external signal with pulse width lower than APB2 clock period. Refer to the
electrical characteristics section of the datasheet for details on this parameter.
9.2.2

Block diagram

The block diagram is shown in

Figure 19. External interrupt/event controller block diagram

9.2.3

Wakeup event management

The STM32F10xxx is able to handle external or internal events in order to wake up the core
(WFE). The wakeup event can be generated either by:
●
enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex-M3 System Control register. When the MCU
resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ
channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
●
or configuring an external or internal EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.
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Figure
PCLK2
20
Interrupt
mask
register
To NVIC Interrupt
20
Controller
20
Pulse
20 generator
20
19.
AMBA APB bus
Peripheral interface
20 20
Software
Pending
interrupt
request
event
register
register
20
20
20
Event
mask
register
20 20
Rising Falling
trigger trigger
selection selection
register register
20 20
Edge detect
circuit
RM0034
Input
Line
ai15801