ST STM32WL55JC Reference Manual page 1114

Inter-integrated circuit (I2C) interface
Bit 10 OVRCF: Overrun/Underrun flag clear
Bit 9 ARLOCF: Arbitration lost flag clear
Bit 8 BERRCF: Bus error flag clear
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 STOPCF: STOP detection flag clear
Bit 4 NACKCF: Not Acknowledge flag clear
Bit 3 ADDRCF: Address matched flag clear
Bits 2:0 Reserved, must be kept at reset value.
34.7.9 I2C PEC register (I2C_PECR)
Address offset: 0x20
Reset value: 0x0000 0000
Access: No wait states
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PEC[7:0]: Packet error checking register
Note: If the SMBus feature is not supported, this register is reserved and forced by hardware to
"0x00000000". Refer to
1114/1454
Writing 1 to this bit clears the OVR flag in the I2C_ISR register.
Writing 1 to this bit clears the ARLO flag in the I2C_ISR register.
Writing 1 to this bit clears the BERRF flag in the I2C_ISR register.
Writing 1 to this bit clears the STOPF flag in the I2C_ISR register.
Writing 1 to this bit clears the NACKF flag in I2C_ISR register.
Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also
clears the START bit in the I2C_CR2 register.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
This field contains the internal PEC when PECEN=1.
The PEC is cleared by hardware when PE=0.
Section 34.3: I2C
24 23 22
Res. Res. Res.
8 7 6
Res.
r r
implementation.
RM0453 Rev 2
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
PEC[7:0]
r r r r
RM0453
17 16
Res. Res.
1 0
r r