ST STM32WL55JC Reference Manual page 1108

Inter-integrated circuit (I2C) interface
34.7.4 I2C own address 2 register (I2C_OAR2)
Address offset: 0x0C
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x
I2CCLK.
31 30 29
Res. Res. Res. Res.
15 14 13
OA2EN Res. Res. Res.
rw
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 OA2EN: Own Address 2 enable
Bits 14:11 Reserved, must be kept at reset value.
Bits 10:8 OA2MSK[2:0]: Own Address 2 masks
Note: These bits can be written only when OA2EN=0.
Bits 7:1 OA2[7:1]: Interface address
Note: These bits can be written only when OA2EN=0.
Bit 0 Reserved, must be kept at reset value.
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28 27 26 25
Res. Res. Res.
12 11 10 9
Res. OA2MSK[2:0]
rw rw
0: Own address 2 disabled. The received slave address OA2 is NACKed.
1: Own address 2 enabled. The received slave address OA2 is ACKed.
000: No mask
001: OA2[1] is masked and don't care. Only OA2[7:2] are compared.
010: OA2[2:1] are masked and don't care. Only OA2[7:3] are compared.
011: OA2[3:1] are masked and don't care. Only OA2[7:4] are compared.
100: OA2[4:1] are masked and don't care. Only OA2[7:5] are compared.
101: OA2[5:1] are masked and don't care. Only OA2[7:6] are compared.
110: OA2[6:1] are masked and don't care. Only OA2[7] is compared.
111: OA2[7:1] are masked and don't care. No comparison is done, and all (except reserved)
7-bit received addresses are acknowledged.
As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and
0b1111xxx) are not acknowledged even if the comparison matches.
7-bit addressing mode: 7-bit address
24 23 22
Res. Res. Res.
8 7 6
rw rw rw
RM0453 Rev 2
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
OA2[7:1]
rw rw rw rw
RM0453
17 16
Res. Res.
1 0
Res.
rw