Reference Clock - Xilinx 7 Series User Manual

Chapter 5: Board Design Guidelines
Table 5-6: Unused GTP Quad Column Connections (Cont'd)
MGTREFCLKP/MGTREFCLKN
MGTRXP/MGTRXN
MGTTXP/MGTTXN
MGTRREF

Reference Clock

Overview
This section focuses on the selection of the reference clock source or oscillator. An oscillator is
characterized by:
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These characteristics are selection criteria when choosing an oscillator for a GTP transceiver design.
Figure 5-4
This figure is provided to show the contrast to the differential clock input voltage swing calculation
shown in
X-Ref Target - Figure 5-4
+V MGTREFCLKP
MGTREFCLKN
0
Figure 5-4: Single-Ended Clock Input Voltage Swing, Peak-to-Peak
224
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Pin or Pin Pair of the Unused GTP Quad
Frequency range
Output voltage swing
Jitter (deterministic, random, peak-to-peak)
Rise and fall times
Supply voltage and current
Noise specification
Duty cycle and duty-cycle tolerance
Frequency stability
illustrates the convention for a single-ended clock input voltage swing, peak-to-peak.
Figure 5-5.
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Connection
Float (if not used)
GND
Float
MGTAVTT through a 100Ω resistor
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Single-ended
Voltage
UG482_c5_04_080612