Xilinx 7 Series User Manual page 60

Chapter 2: Shared Features
RX Rate Change
In most cases, in addition to changing the output divider, an RX rate change requires changing the
RX CDR loop filter settings via DRP (See
setting and updating the RX_OUTDIV attribute via DRP, the RX must be reset by toggling the
GTRXRESET port. In cases where the CDR loop filter does not need to be updated via DRP, rate
change can be performed using the RXRATE port with RXRATEMODE set to 1'b0. As a result,
the required reset sequence is performed automatically. When RXRATEDONE is asserted in
response to RXRATE, it indicates both rate change and the necessary reset sequence has been
applied and completed.
If RX buffer is enabled, RXBUF_RESET_ON_RATE_CHANGE attribute should be set to "TRUE"
to allow RX buffer to reset automatically after rate change when using the RXRATE port. If RX
buffer bypass mode is used, alignment must be repeated after RXRATEDONE is asserted.
RX Parallel Clock Source Reset
The clocks driving RXUSRCLK and RXUSRCLK2 must be stable for correct operation. These
clocks are often driven from an MMCM in the FPGA to meet phase and frequency requirements. If
the MMCM loses lock and begins producing incorrect output, RXPCSRESET should be toggled
after the clock source relocks. If RX buffer bypass mode is used, alignment must be repeated after
the completion of the reset procedure.
After Remote Power-Up
If the source of incoming data is powered up after the GTP transceiver that is receiving its data is
operating, the RX side must be reset to ensure a clean lock to the incoming data
Electrical Idle Reset
For protocols that support OOB and electrical idle, when the differential voltage of the RX input to
the transceiver drops to OOB or electrical idle levels, the RX CDR will be managed automatically
when attributes associated with electrical idle are set to appropriate values. Recommended values
from the 7 Series FPGA Transceivers Wizard should be used.
After Connecting RXN/RXP
When the RX data to the GTP transceiver comes from a connector that can be plugged in and
unplugged, the RX side must be reset when the data source is plugged in to ensure that it can lock to
incoming data.
After Recovered Clock Becomes Stable
Depending on the design of the clocking scheme, it is possible for the RX reset sequence to be
completed before the CDR is locked to the incoming data. In this case, the recovered clock may not
be stable when RXRESETDONE is asserted. When RX buffer is used, RXBUFRESET should be
triggered after the recovered clock becomes stable. When RX buffer bypass is used, the alignment
procedure should not start until the recovered clock becomes stable. Refer to DS181, Artix-7 FPGAs
Data Sheet for successful CDR lock-to-data criteria.
After an RX Elastic Buffer Error
After an RX elastic buffer overflow or underflow, the RX elastic buffer must be reset using
RXBUFRESET to ensure correct behavior.
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RX CDR). After writing in the proper RX CDR loop filter
www.xilinx.com 7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016