Xilinx 7 Series User Manual page 225

Figure 5-5
MGTREFCLKP - MGTREFCLKN and used in the GTP transceiver portion of the Artix-7 FPGA
data sheet.
X-Ref Target - Figure 5-5
+V MGTREFCLKP - MGTREFCLKN
0
–V
Figure 5-5: Differential Clock Input Voltage Swing, Peak-to-Peak
Figure 5-6
X-Ref Target - Figure 5-6
80%
20%
Figure 5-7
input pair MGTREFCLKP/MGTREFCLKN is internally terminated with 100Ω differential
impedance. The common mode voltage of this differential reference clock input pair is 4/5 of
MGTAVCC, or nominal 0.8V. Refer to DS181, Artix-7 FPGAs Data Sheet: DC and Switching
Characteristics for exact specifications.
X-Ref Target - Figure 5-7
MGTREFCLKP
MGTREFCLKN
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
illustrates the differential clock input voltage swing, peak-to-peak, which is defined as
shows the rise and fall time convention of the reference clock.
T
RCLK
T
FCLK
Figure 5-6: Rise and Fall Time
illustrates the internal details of the IBUFDS. The dedicated differential reference clock
Ω
(1)
50
4/5 MGTAVCC
Ω
(1)
50
Figure 5-7: MGTREFCLK Input Buffer Details
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Reference Clock
UG482_c5_06_080612
To GTP
Dedicated
Clock
REFCLK
Routing
UG482_c5_07_080612
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V
IDIFF
UG482_c5_05_072412
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