Xilinx 7 Series User Manual page 68

Chapter 2: Shared Features
Table 2-30: DRP Ports of GTPE2_COMMON
DRPADDR[7:0]
DRPCLK
DRPEN
DRPDI[15:0]
DRPRDY
DRPDO[15:0]
DRPWE
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Port Dir Clock Domain
In DRPCLK
In
In DRPCLK
In DRPCLK
Out DRPCLK
Out DRPCLK
In DRPCLK
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DRP address bus.
N/A DRP interface clock.
DRP enable signal.
0: No read or write operation performed.
1: Enables a read or write operation.
For write operations, DRPWE and DRPEN must
be driven High for one DRPCLK cycle only (see
Figure 2-23 for correct operation). For read
operations, DRPEN must be driven High for one
DRPCLK cycle only (see
operation).
Data bus for writing configuration data from the
FPGA logic resources to the transceiver.
Indicates operation is complete for write
operations and data is valid for read operations.
Data bus for reading configuration data from the
GTP transceiver to the FPGA logic resources.
DRP write enable.
0: Read operation when DRPEN is 1.
1: Write operation when DRPEN is 1.
For write operations, DRPWE and DRPEN must
be driven High for one DRPCLK cycle only.
Please see Figure 2-23
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Description
Figure 2-24 for correct
for correct operation.