Tx Buffer - Xilinx 7 Series User Manual

TX Buffer

Functional Description
The GTP transceiver TX datapath has two internal parallel clock domains used in the PCS: the PMA
parallel clock domain (XCLK) and the TXUSRCLK domain. To transmit data, the XCLK rate must
match the TXUSRCLK rate, and all phase differences between the two domains must be resolved.
Figure 3-11
X-Ref Target - Figure 3-11
TX Serial Clock
TX TX
TX OOB Pre/
Driver
and Post
PCIe Emp
TX Clock
Dividers
TX Phase
Interpolator
TX PMA
Clock from PLL0 or PLL1
The GTP transceiver transmitter includes a TX buffer and a TX phase alignment circuit to resolve
phase differences between the XCLK and TXUSRCLK domains. The TX phase alignment circuit is
used when TX buffer is bypassed (see
either the TX buffer or the TX phase alignment circuit.
buffering and phase alignment.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
shows the XCLK and TXUSRCLK domains.
PMA Parallel Clock (XCLK)
PCIe
Beacon
Polarity
PISO
TX PCS
To RX Parallel Data
(Near-End PCS Loopback)
Figure 3-11: TX Clock Domains
www.xilinx.com
PCS Parallel Clock (TXUSRCLK)
SATA
OOB
Pattern
Generator
Phase
Adjust
FIFO
From RX Parallel Data
(Far-End PMA Loopback)
TX Pattern Generator, page
Table 3-12
TX Buffer
FPGA Parallel
Clock
(TXUSRCLK2)
TX
Gearbox
TX PIPE
Control
FPGA
TX
Interface
8B/10B
Encoder
TX Phase
Interpolator
Controller
From RX Parallel Data
(Far-End PCS Loopback)
UG482_C3_14_112811
103). All TX datapaths must use
shows trade-offs between
Send Feedback
93