Xilinx 7 Series User Manual page 300

Appendix D: DRP Address Map of the GTP Transceiver
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
1:0
007C
15
007D
14
007D
13:0
007D
15
007E
3:0
007E
4
0081
3:0
0081
15:0
0082
15:0
0083
15:0
0086
7:0
0087
15
0088
14:11
0088
6:4
0088
2:0
0088
15:0
0089
15:0
008A
10:0
008B
6:0
008C
15:13
008D
12
008D
11:10
008D
9:5
008D
4:0
008D
15
008E
300
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R/W Attribute Name
R/W PMA_RSV3
R/W PMA_RSV7
R/W PMA_RSV6
R/W TX_RXDETECT_CFG
R/W CLK_COMMON_SWING
R/W RX_CM_TRIM
R/W RXLPM_CFG1
R/W RXLPM_CFG
R/W PMA_RSV2
R/W PMA_RSV2
R/W DMONITOR_CFG
R/W DMONITOR_CFG
R/W RXLPM_BIAS_STARTUP_DISABLE
R/W RXLPM_HF_CFG3
R/W TXOUT_DIV
R/W RXOUT_DIV
R/W CFOK_CFG
R/W CFOK_CFG
R/W CFOK_CFG
R/W CFOK_CFG3
R/W RXPI_CFG0
R/W RXLPM_CM_CFG
R/W CFOK_CFG5
R/W RXLPM_LF_CFG2
R/W RXLPM_HF_CFG2
R/W RXLPM_IPCM_CFG
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Attribute Attribute
Bits Encoding
1:0 0-3
0 0-1
0 0-1
13:0 0-16383
0 0-1
3:0 0-15
0 0-1
3:0 0-15
15:0 0-65535
31:16 0-65535
15:0 0-65535
23:16 0-255
0 0-1
3:0 0-15
1
2
2:0
4
8
1
2
2:0
4
8
15:0 0-65535
31:16 0-65535
42:32 0-2047
6:0 0-127
2:0 0-7
0 0-1
1:0 0-3
4:0 0-31
4:0 0-31
0 0-1
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
DRP
Encoding
0-3
0-1
0-1
0-16383
0-1
0-15
0-1
0-15
0-65535
0-65535
0-65535
0-255
0-1
0-15
0
1
2
3
0
1
2
3
0-65535
0-65535
0-2047
0-127
0-7
0-1
0-3
0-31
0-31
0-1